> NMI does not do an INTA cycle ! > Where do routine exits go ? > How do calling routines identify completion status ? Micro Decision HD Hard Disk Low Level Firmware Thå  lo÷  leveì harä disë read/writå firmwarå requireó  preciså synchonizatioî  betweeî  rom¬  raí anä proí  code®  Somå  oæ  thå objectiveó  foò thió codå arå tï havå thå datá buffeò anä  headeò imagå  falì  iî thå samå raí locatioî foò readinç  anä  writting® Sincå botè routineó begiî witè finä sector¬ iô shoulä bå possiblå to have the same entry address. Thå  Z8°  musô accesó á bytå oæ memorù belo÷ 800° tï  turî  ofæ AUTO® Sincå commoî ió smalleò thaî 32K¬ wherå doeó thå stacë pusè puô  thå returî addresó duå tï thå interruptó ¿  INÔ doeó aî INTÁ whicè wilì cleaò AUTÏ buô NMÉ doeó not® Coulä /MATCÈ anä /TIMEOUÔ be ORed ? How would the interrupt be evaluated ? AUTO EQU 0F7E0 ;ENTRY FOR READ OR WRITE COLD: ;CLEAR LATCH ORG 66 ;NMI ADDRESS NMI: POP D ;GET POINTER RNC ;EXIT AUTO IF A HEADER EI ;ELSE ENABLE INTERRUPS JMP AUTO ;AND TRY AGAIN ORG 38 ;INT ADDRESS IN MODE 1 INT: POP D ;GET POINTER DEC (IY) ;DCR REV COUNT RZ ;EXIT AUTO IF ZERO EI ;ELSE ENABLE INTERRUPTS JMP AUTO ;AND TRY AGAIN \ \ A U T O \ \ HL 17E3 PCHL TARGET FOR READ SYNC \ C SIZE BYTES/SECTOR / 32 \ \ LATCH RAM, READ, CMPR, MARK, PROM \ \ REVS 2 REVOLUTIONS COUNT FOR TIMEOUT \ \ INTERRUPT MODE1 \ INTERRUPTS ENABLED \ Š\ TARGET HEADER IMAGE AT 17E4-17E7 \ \ LAST BYTE OF BUFFER COPIED TO ? \ \ SELECT SECTOR SIZE 3 IN COMMAND REGISTER \ \ EPROM LOCATION ARE RELATIVE TO ERPOM SIZE - 200H. \ \ R E A D S E C T O R - O P 0 \ \ AT 000 - 080 IN ERPOM \ \ The control word RAM, READ, COMPARE, MARK must be loaded into \ the latch prior to execution. Following execution, the last three \ bytes read will be stored in ram at FC00-FC02 and will have to be \ moved back to the end of the physical buffer. \ \ Before The Data Field 000 - 01F \ ADDR RAM BUS R C M P L EPROM COMMENT F7E0 RAM 0 0 0 1 1 00 ;nop - allign for SYNC F7E1 RAM 0 0 0 1 1 3F ;scf - implies not header F7E2 A1 RAM 1 0 0 0 0 E9 ;pchl - loop until sync F7E3 FE RAM 1 1 0 1 1 B7 ;ora a - header, clr cry F7E4 00 RAM 1 1 0 1 1 00 ;nop F7E5 00 RAM 1 1 0 1 1 00 ;nop F7E6 00 RAM 1 1 0 1 1 00 ;nop F7E7 00 CRC 1 1 0 1 1 00 ;nop F7E8 CRC 1 1 0 1 1 00 ;nop F7E9 RAM 1 1 0 1 1 21 ;lxi h, F7EA RAM 1 0 0 1 1 0D ; data F7EB RAM 0 0 0 1 1 F7 ; pchl+1 F7EC A1 RAM 1 0 0 0 0 E9 ;pchl - loop until sync F7ED F8 SR 1 1 0 1 1 C3 ;jmp F7EE SR 1 0 0 1 1 00 ; around F7EF SR 1 0 0 1 1 F8 ; write \ In The Data Field 020 - 03F \ ADDR RAM BUS R C M P L EPROM COMMENT F800 SR 1 0 0 1 1 00 ;nop F801 SR 1 0 0 1 1 00 ;nop F802 SR 1 0 0 1 1 00 ;nop F818 SR 1 0 0 1 1 00 ;nop F819 SR 1 0 0 1 1 0D ;dcr c F81A SR 1 0 0 1 1 CA ;jz F81B SR 1 0 0 1 1 00 ; after F81C SR 1 0 0 1 1 FC ; data field F81D SR 1 0 0 1 1 00 ;nop F81E SR 1 0 0 1 1 00 ;nop F81F SR 1 0 0 1 1 00 ;nop Š \ After The Data Field 060 - 07F \ ADDR RAM BUS R C M P L EPROM COMMENT FC00 CRC 1 0 0 1 1 00 ;nop FC01 CRC 1 1 0 1 1 00 ;nop FC02 00 RAM 1 1 0 1 1 00 ;jmp FC03 00 RAM 1 0 0 1 1 00 ;addr FC04 00 RAM 0 0 0 1 1 00 ;addr \ \ W R I T E S E C T O R - O P 1 \ \ AT 080 - 100 IN ERPOM \ \ The control word RAM, READ, COMPARE, MARK must be loaded into Ü thå latcè prioò tï executioî anä thå lasô bytå of the physical \ buffer must be copied to FC00. \ \ Before The Date Field 080 - 09F \ RAM BUS R C M P L EPROM COMMENT F7E0 RAM 0 0 0 1 1 00 ;nop - allign for SYNC F7E1 RAM 0 0 0 1 1 3F ;scf - implies not header F7E2 A1 RAM 1 0 0 0 0 E9 ;pchl - loop until sync F7E3 FE RAM 1 1 0 1 1 B7 ;ora a - header, clr cry F7E4 00 RAM 1 1 0 1 1 00 ;nop F7E5 00 RAM 1 1 0 1 1 00 ;nop F7E6 00 RAM 1 1 0 1 1 00 ;nop F7E7 00 CRC 1 1 0 1 1 00 ;nop F7E8 CRC 1 1 0 1 1 C3 ;jmp F7E9 RAM 1 1 0 1 1 F7 ; around F7EA RAM 1 0 0 1 1 F7 ; write \ SKIP AROUND START OF READ SECTOR F7F7 00 RAM 0 0 0 1 1 16 ;mvi d, F7F8 00 RAM 0 1 0 1 1 03 ; 3 F7F9 00 RAM 0 1 0 1 1 15 ;dcr d F7FA 00 RAM 0 1 0 1 1 C2 ;jnz F7FB 00 RAM 0 1 0 1 1 F9 ; loop for F7FC 00 RAM 0 1 0 1 1 F7 ; preamble F7FD 00 RAM 0 1 0 1 1 00 ;nop F7FE A1 RAM 0 1 1 0 1 00 ;nop F7FF F8 RAM 0 1 0 1 1 00 ;nop \ In The Data Field 0A0 - 0BF \ ADDR RAM BUS R C M P L EPROM COMMENT F800 E5 RAM 0 1 0 1 1 00 ;nop F801 E5 RAM 0 1 0 1 1 00 ;nop ŠF802 E5 RAM 0 1 0 1 1 00 ;nop F81B E5 RAM 0 1 0 1 1 0D ;dcr c F81C E5 RAM 0 1 0 1 1 CA ;jz F81D E5 RAM 0 1 0 1 1 00 ;addr F81E E5 RAM 0 1 0 1 1 FC ;addr F81F E5 RAM 0 1 0 1 1 00 ;nop \ After The Data Field 0E0 - 0FF \ ADDR RAM BUS R C M P L EPROM COMMENT FC00 CRC 0 1 0 1 1 00 ;nop FC01 CRC 0 1 0 1 1 00 ;nop FC02 RAM 0 1 0 1 1 00 ;nop FC03 00 RAM 0 1 0 1 1 00 ;jmp FC04 00 RAM 0 1 0 1 1 00 ;addr FC05 00 RAM 0 0 0 1 1 00 ;addr \ \ R E A D H E A D E R - O P 2 \ \ AT 100 - 180 IN ERPOM \ \ The control word RAM, READ, COMPARE, MARK must be loaded into \ the latch prior to execution. Following execution, the last three \ bytes read will be stored in ram at FC00-FC02 and will have to be \ moved back to the end of the physical buffer. \ \ Before The Data Field 100 - 11F \ ADDR RAM BUS R C M P L EPROM COMMENT F7E0 RAM 0 0 0 1 1 00 ;nop - allign for SYNC F7E1 RAM 0 0 0 1 1 00 ;nop F7E2 A1 RAM 1 0 0 0 0 E9 ;pchl - loop until sync F7E3 FE SR 1 1 0 1 1 C3 ;jmp F7E4 SR 1 1 0 1 1 00 ; data F7E5 SR 1 0 0 1 1 F8 ; field \ In The Data Field 120 - 13F \ ADDR RAM BUS R C M P L EPROM COMMENT F800 SR 1 0 0 1 1 00 ;nop F801 CRC 1 0 0 1 1 00 ;nop F802 CRC 1 0 0 1 1 00 ;nop F803 RAM 1 1 0 1 1 00 ;nop F804 RAM 1 1 0 1 1 C3 ;jmp F805 RAM 1 0 0 1 1 00 ; addr F806 RAM 0 0 0 1 1 00 ; addr \ Š\ F O R M A T T R A C K - O P 3 \ \ AT 180 - 200 IN EPROM \ Ü Formaô wilì uså á tablå oæ sectoò numberó iî onå oæ thå fouò 3² Ü bytå blockó oæ memorù associateä witè thå command® Thå singlå Ü bytå wilì bå loadeä througè thå uså oæ á loaä indirecô Ü instructioî Á :½ (HL)® Thå balacå oæ FORMAÔ requireó morå thaî Ü 3² byteó oæ codå anä wilì probablù involvå thå CPÕ jumpinç \ betweeî twï blocks. \ \ Write 16 bytes of 4E at start of track \ ADDR RAM BUS R C M P L EPROM COMMENT F7E0 RAM 0 0 0 1 1 16 ;mvi d, F7E1 4E RAM 0 1 0 1 1 03 ; 3 F7E2 4E RAM 0 1 0 1 1 15 ;dcr d F7E3 4E RAM 0 1 0 1 1 C2 ;jnz F7E4 4E RAM 0 1 0 1 1 E2 ; loop for F7E5 4E RAM 0 1 0 1 1 F7 ; gap1 F7E6 4E RAM 0 1 0 1 1 16 ;mvi d, F7E7 4E RAM 0 1 0 1 1 03 ; 3 \ Write N sectors \ Write preampble and header \ RAM BUS R C M P L EPROM COMMENT F7E8 00 RAM 0 1 0 0 0 15 ;dcr d F7E9 00 RAM 0 1 0 0 0 C2 ;jnz F7EA 00 RAM 0 1 0 0 0 00 ;addr F7EB 00 RAM 0 1 0 0 0 00 ;addr A1 RAM 0 1 0 1 0 00 ; FE RAM 0 1 1 0 0 00 ; 00 RAM 0 1 0 0 0 00 ; 00 RAM 0 1 0 0 0 00 ; 00 RAM 0 1 0 0 0 7E ;mov a,m CRC 0 1 0 0 0 00 ;mvi d, CRC 0 1 0 0 0 00 ; 3 00 RAM 0 1 0 0 0 00 ;jmp 00 RAM 0 1 0 0 0 00 ;addr 00 RAM 0 1 0 0 0 00 ;addr \ Second 32 byte block of code \ Write preamble and data field \ RAM BUS R C M P L EPROM COMMENT 00 RAM 0 1 0 0 0 15 ;dcr d 00 RAM 0 1 0 0 0 C2 ;jnz 00 RAM 0 1 0 0 0 00 ;addr 00 RAM 0 1 0 0 0 00 ;addr A1 RAM 0 1 0 1 0 00 ;mvi d, F8 RAM 0 1 1 0 0 00 ; 0 Š E5 RAM 0 1 0 0 0 00 ;dcr d E5 RAM 0 1 0 0 0 00 ;jnz E5 RAM 0 1 0 0 0 00 ;addr E5 RAM 0 1 0 0 0 00 ;addr CRC 0 1 0 0 0 00 ; CRC 0 1 0 0 0 00 ; 00 RAM 0 1 0 0 0 00 ; 00 RAM 0 1 0 0 0 00 ; 00 RAM 0 1 0 0 0 00 ; \ Write Gap 3 \ RAM BUS R C M P L EPROM COMMENT 4E RAM 0 1 0 1 0 00 ;mvi d, 4E RAM 0 1 1 0 0 00 ; 0 4E RAM 0 1 0 0 0 00 ;dcr d 4E RAM 0 1 0 0 0 00 ;jnz 4E RAM 0 1 0 0 0 00 ;addr 4E RAM 0 1 0 0 0 00 ;addr 4E RAM 0 1 0 0 0 00 ;dcr d 4E RAM 0 1 0 0 0 00 ;jnz 4E RAM 0 1 0 0 0 00 ;addr 4E RAM 0 1 0 0 0 00 ;addr \ Write 4E until end of track \ RAM BUS R C M P L EPROM COMMENT 4E RAM 0 1 0 1 0 C3 ;jmp 4E RAM 0 1 1 0 0 00 ;addr 4E RAM 0 1 0 0 0 00 ;addr Determinå allignmenô oæ reaä anä writå codå foò á fixeä locatioî buffer® Notå thaô reaä anä writå operationó wilì requirå patchinç aô thå enä oæ thå datá buffer. RAM D1 D2 D3 Disk Read SR F8 D1 D2 D3 PROM SR SR SR Disk Write SR A1 F8 D1 D2 D3 BUS RAM RAM RAM PROM RAM RAM RAM ŠREAD/WRITE CHECK LIST: > Disable Z80 peripheral interrupts and enable interrupt mode 1. > Initialize ram images of header, preampble and postamble. > Patch end of data field for read or write. > Set bank register for AUTO ENA and ROM. > Initialize control latch for read sync. > Initialize mode register including op code and precomp bit. >  Initializå drivå registeò includinç drive¬  heaä selectioî anä    low current bit. > Initialize revolutions count. > Check drive ready. > Perform required seeking. FILE: AUTO.TXT DISK: UD3 DATE: 5/4/83