; PROJECT	MICRO DECISION HD
; FUNCTION	FPLS - DISK CONTROL 
; BY		MICHAEL STOLOWITZ
; FILE 		FPLS.TXT
; DISK		uD3
; REVISION	5/5/83
;               5/6/83 DEFINED PIN NUMBERS
;		5/     MARK-BIT CHANGES
;		5/10/83 inhibit sync on /auto
; 		5/11/83 removed /read form clear hang
;		5/13/83 qualified SYNC0-S with /SYNC0
;		5/13/83 delay MARK-BIT one more bit time
;		5/17/83 SYNC clears ready one bit time early for
;		floppy reads.
;		5/17/83 correct mark clear for read/write
;		8/12/83 correct missing clock position for A1 for
;		double density floppies.
;		9/14/82 Clear external SYNC between M1 cycles.
;		9/20/83 Added new term to clear floppy read
;		application of SYNC after one clock cell. Also
;		qualified the hard disk /M1 term with AUTO.
;		9/24/83 Deleted old SYNC-C2 term, and renamed
;		SYNC-C3	to SYNC-C2.
;		Extended change of 9/14/83 to floppies.
;		11/16/83 Qualified SYNC-S with RUN
;
82S105


I0   T3			( BIT COUNTER MSB ) 
I1   T1			( BIT COUNTER     )
I2   RUN		( AUTO )
I3  /CLK-I		( /CLK OUTPUT   )
I4   SR0		( SR BUS SOURCE )
I5   SR1		( SR BUS SOURCE )
I6   START		( FIELD 00 DATA )
I7   SEP-DATA		( SEPARATED DATA )
I8   /M1		( Z-80 M1 )
I9   AUTO		( AUTO-ENA)
I10  ALT		( ALTERNATE MARK )
I11  MFM		( MFM/FM )
I12  MARK-BYTE		
I13  READ		
I14  T2			( BIT COUNTER     )
I15  T0			( BIT COUNTER LSB )

F0  /SYNC		( PRE-BYTE PULSE  )
F1   S0			( SR CONTROL LSB  )
F2  /HANG		( CLEAR AND HOLD BIT COUNTER    )
F3  /BYTE		( BYTE PULSE      )
F4  /VCO		( ENABLE PLL	  ) 
F5  /MARK		( RD - ERROR / WR - STEAL CLOCK )
F6   S1			( SR CONTROL MSB  )
F7  /CLK		( DATA/CLOCK CELL )

P0   CRC		( GENERATE/CHECK CRC            ) 
�P1   (MARK1)		( NRZ CLOCK PATTERN 	        )
P2   SYNC0		( SYNC STATE LSB  )
P3   SYNC1		( SYNC STATE MSB  )
P4   (MARK2)
P5   SR-ENA		( SHIFT REGISTER ENABLE )


COMP COMPLEMENT


TERM SR-ENA-S   T2    T1   / T0   / /CLK-I    SR1

TERM SR-ENA-C   T2    T1   / T0   / /CLK-I  / SR1 

;  SHIFT REGISTER CONTROLS 

TERM CRC-S	T2    T1   / T0   / /CLK-I     SR0

TERM CRC-C	T2    T1   / T0   / /CLK-I   / SR0

	( CRC load SR0 in bit 6 clock )

TERM S0-S1 	 /CLK-I   / CRC   / READ

	( Set S0 on /CLK if /CRC if not in READ )

TERM S0-S2 	 /CLK-I   / CRC     SYNC1

	( Set S0 on /CLK if /CRC if READ and SYNC )

TERM S1-S1	 /CLK-I   T2   T1   T0   / SR1   / SR0   / READ

	( Set S1 on /CLK of bit 7 if /SR1 and /SR0 if not READ )

TERM S1-S2	 /CLK-I   T2   T1   T0   / SR1   / SR0     SYNC1

	( Set S1 on /CLK of bit 7 if /SR1 and /SR0 if READ and SYNC )

TERM S1-S3	 /CLK-I   CRC

	( Set S1 on /CLK if CRC )

	( 7 terms, 2 outputs, 1 internal ) 


; MARK GENERATION AND DETECTION 

TERM BIT0-1	/ AUTO   / MFM   / T2   / T1   / T0   / /CLK-I   SYNC1 

	( D7 or C7 clock in READ and SYNC )

TERM BIT0-2	/ AUTO   / MFM   / T2   / T1   / T0   / /CLK-I   / READ 

	( D7 or C7 clock in WRITE )

�TERM BIT1	/ AUTO   / MFM    ALT   / T2   / T1     T0   / /CLK-I

	( C7 clock )

TERM BIT2-1     / AUTO   / MFM   / T2     T1   / T0   / /CLK-I

	( D7 or C7 clock )

TERM BIT2-2	/ AUTO   / ALT   / T2     T1   / T0   / /CLK-I

	( D7 or 3-4 clock )

TERM BIT3-1	/ AUTO	   MFM	  ALT	/ T2	 T1	 T0	/ /CLK-I

	( 4-5 clock )

TERM BIT3-2	  AUTO           / T2     T1     T0   / /CLK-I

	( 4-5 clock for hard disk A1* )

TERM (MARK1)-C     COMPLEMENT   / /CLK-I

	( Set internal MARK on selected bit true and end bit )
	
	( Use complement to clear at end of bit if all false )

TERM (MARK2)-S	    (MARK1)  / /CLK-I

TERM (MARK2)-C    / (MARK1)  / /CLK-I

	( Follow mark1 by 1 bit time )

TERM MARK-S1	  MARK-BYTE  (MARK1)   READ   SEP-DATA    /CLK-I

	( In READ, set if mark clock is present - i.e. error )

TERM MARK-S2	  MARK-BYTE  (MARK2)  / READ   / /CLK-I

	( In WRITE, follow internal MARK by one bit time )

TERM MARK-C1	/ (MARK1)   / /CLK-I    READ

	( Follow internal mark1 down for a read )

TERM MARK-C2   / (MARK2)    / /CLK-I   / READ  

	( Follow internal mark2 down for a write )

	( 9 terms, complement, 1 output, 1 internal )


; READ SYNCHRONIZATION 

TERM CLK	/ /CLK-I

�	( Second half of any bit )


TERM BYTE-S1	 /CLK-I  T2  T1  T0  

	( Set on first half of bit 7 )

TERM BYTE-C1	 / /CLK-I  / READ

	( Clear in second half of bit 7 if /READ )

TERM BYTE-C2	/ /CLK-I  SYNC1  T2  T1  T0

	( Clear in second half of bit 7 if in sync )

	( Clears on entering sync )


TERM SYNC0-S	 READ  T3  T2  T1  T0  / /CLK-I  / SYNC0

	( READ and two bytes of 00 data )

TERM SYNC1-S	 READ  SYNC0  / /CLK-I  SEP-DATA  / SYNC1

	( READ and SYNC0 and 1 data bit )

TERM SYNC-C1	 AUTO  READ  SYNC0  SYNC1 /M1

	( Clear SYNC given read sync of hard disk, but not during M1 )

TERM SYNC-S2     / AUTO  SYNC1  READ  / /CLK-I  T2 T1 / T0 SR-ENA

	( READ and SYNC1 not auto, last half of bit 6 )

TERM SYNC-C2     / AUTO  SYNC1  READ  T2 T1 T0  /M1

	( READ and SYNC1 not auto, bit 7, but not during /M1 )

TERM SYNC-C3	/ AUTO SYNC1 READ / T2 / T1 / T0 /M1

	( READ and SYNC1 not auto, bit 0, but not during /M1 )

TERM /READ	/ READ

	( Not READ )

TERM SYNC-S	 READ  / SYNC0  / SYNC1  RUN

	( Start of READ for hard disk )

TERM VCO-S1	 READ  / SYNC0  / SYNC1  AUTO    START

	( Wait for high frequency data if hard disk )

TERM VCO-C1	 READ  / SYNC0  / SYNC1  AUTO  / START
�
	( Clear on loss of high frequency data )

TERM VCO-S2	 READ  / SYNC0  / SYNC1  / AUTO

	( Enable immediately if floppy )

TERM /CLK-S1 	/ READ  /CLK-I

	( Toggle if not READ )

TERM /CLK-S2	  SYNC0  /CLK-I

	( Toggle if SYNC0 )

TERM /CLK-S3	  READ  / SYNC0   /CLK-I  SEP-DATA

	( Set on clock transition in READ and / SYNC0 )


TERM /HANG-S1  	AUTO  / RUN

	( In AUTO, stall if not RUN )

TERM /HANG-S2	AUTO  READ  / SYNC0  / START

	( If AUTO and not SYNC, wait for START )

TERM /HANG-S3	READ  / SYNC0  /CLK-I  / SEP-DATA

	( If not synced, set on missed clock )

TERM /HANG-C1	RUN  / READ

	( Clear if RUN and  / READ for AUTO )

TERM /HANG-C2	/ AUTO  / READ

	( or /READ for /AUTO )

TERM /HANG-C3	READ  / SYNC0  START  /CLK-I  SEP-DATA

	( Clear on clock transition and START if AUTO )

TERM /HANG-C4	READ  / SYNC0  / AUTO  /CLK-I  SEP-DATA

	( or just clock transition if /AUTO )		


; Internal States 

SET SR-ENA	SR-ENA-S
CLR SR-ENA	SR-ENA-C

SET CRC		CRC-S
�CLR CRC		CRC-C

SET (MARK1)	BIT0-1  BIT0-2  BIT1  BIT2-1  BIT2-2  BIT3-1 BIT3-2
CLR (MARK1)	(MARK1)-C

SET (MARK2)	(MARK2)-S
CLR (MARK2)	(MARK2)-C

SET SYNC0	SYNC0-S
CLR SYNC0	/READ

SET SYNC1	SYNC1-S
CLR SYNC1	/READ

SET COMPLEMENT	BIT0-1  BIT0-2  BIT1  BIT2-1  BIT2-2  BIT3-1 BIT3-2


; Outputs 

SET S0		S0-S1  S0-S2
CLR S0		CLK

SET S1		S1-S1  S1-S2  S1-S3
CLR S1		CLK

SET /MARK	MARK-C1  MARK-C2
CLR /MARK	MARK-S1  MARK-S2

SET /BYTE	BYTE-C1  BYTE-C2   SYNC1-S
CLR /BYTE	BYTE-S1

SET /SYNC	SYNC-C1	/READ  SYNC-C2 SYNC-C3
CLR /SYNC	SYNC-S   SYNC-S2

SET /VCO	VCO-C1  /READ
CLR /VCO	VCO-S1  VCO-S2

SET /CLK	CLK
CLR /CLK	/CLK-S1  /CLK-S2  /CLK-S3

SET /HANG	/HANG-C1  /HANG-C2  /HANG-C3  /HANG-C4  SYNC1-S  
CLR /HANG	/HANG-S1  /HANG-S2  /HANG-S3   SYNC0-S


END

4/18/83

  Revise� HAN� t� stal� cloc� i� AUT� i� enable� an� RU� i� no� �
asserted� Whe� ru� i� asserted� th� firs� BYT� puls� wil� no� �
occu� fo� on� ful� byt� time.

  BYT� ha� bee� modifie� t� se� i� th� firs� hal� o� bi� � o� �
ever� byte� I� wil� clea� i� no� reading� i� readin� an� i� syn� �
o� o� enterin� sync.
�
  Th� shif� registe� control� S� an� S� hav� bee� modifie� t� �
inhibi� shiftin� durin� th� rea� syn� process� Th� shif� registe� �
wil� b� stalle� fro� th� assertio� o� rea� unti� th� en� o� th� �
firs� bi� tim� o� th� firs� byt� read.

  Adde� � ne� inpu� "RUN� equa� t� AUT� wher� th� curren� inpu� �
"AUTO� i� actaull� AUT� ENA.

5/5/83

  Change CLK to toggle.

5/10/83

  Inhibit SYNC output on /AUTO. Floppy will not use PCHL loop.

5/11/83

  Removed /READ from OR function which cleared HANG. 

5/11/83

  Added missing C3, C4 and S3 terms to HANG.
 
5/13/83

  Qualifie� SYNC0-� wit� � SYNC� t� preven� settin� o� HAN� ever� �
tw� byt� times.

8/12/83

  Added BIT3-1 term and renamed BIT3 to BIT3-2 to position the
missing clock transition correctly for double density floppy
A1 mark.

9/14/83

  Releas� externa� SYN� betwee� M� cycle� eliminatin� th� �
externa� DF� calle� REA� SYNC. READ SYNC becomes SYNC.

9/24/83

  Term SYNC-C3 had not been incorporated into output equations,
and term SYNC-C2 was extraneous. Old term SYNC-C2 was removed
and SYNC-C3 renamed SYNC-C2. Change of 9/14/83 extended to
floppies.

11/03/83

  Canno�� rea� singl� densit� floppy��  BIT� i� tru� throug� th� �
rea� syn� process��  MAR� set� i� th� firs� bi� time��  Qualifie� �
BIT0 with SYNC1 or /READ.  Used last term !