\ PROJECT UD3 \ FUNCTION DRAM PAL \ BY MICHAEL STOLOWITZ & HOWARD FULLMER \ FILE DRAM.TXT \ DISK UD3 \ REVISION 1/31/84 PALS 20R4 1. CLK \ 8 Mhz 2. /HIGH-ROM \ Common Bank or ROM 3. /READ \ Read Strobe 4. AUTO \ Hard Disk R/W Active 5. /ROM-ENB \ Rom enable 6. /READ-SYNC \ Hard Disk Syncing 7. /SYNC-ENA \ Byte Synchronized Access 8. /MREQ \ Memory Request 9. MUX \ Dram Address Mux 10. BANK2 \ Bank Select 11. /READY \ End of Disk Byte 12. GND 13. /OE 14. DSR1 \ Delayed Shift Register Enable 15. /MWE \ Memory Write Enable 16. A15 \ Address bit A15 17. /RAS-INH \ Ras Inhibit ( Internal ) 18. /WAIT \ Z80 wait line 19. /MCAS2 \ Memory Bank 2 CAS 20. /MCAS1 \ Memory Bank 1 CAS 21. /MRAS \ Memory RAS 22. /ROM-OE \ ROM output enable 23. XFER \ Inter-bank transfer enable 24. VCC / /ROM-OE = HI ( Tri-State enable ) + / /MREQ * / /HIGH-ROM * / A15 * / /ROM-ENB * / /READ * / /RAS-INH * / AUTO ( Start normal Z80 access of ROM ) + / /MREQ * / /READ * / /ROM-OE * /WAIT * MUX ( Latch until end of normal Z80 access of ROM ) + AUTO * / /MREQ * / /READ * /WAIT * /READ-SYNC * MUX + AUTO * / /MREQ * / /READ * /WAIT * / /READ-SYNC * / /RAS-INH ( In AUTO enable but only during ) ( /WAIT because of multiplexed bus ) / /MWE = HI ( Tri-State enable ) + /READ * / /MRAS * MUX * / AUTO ( Z80 write status ) Š + AUTO * DSR1 * /MCAS1 * /MCAS2 ( Hard Disk memory write, don't change during CAS ) + AUTO * / /MWE * MUX ( Latch through MUX ) / /WAIT = / /SYNC-ENA * /READY ( Floppy byte synchronized access ) + AUTO * /READY ( Every hard disk cycle except in read sync ) + AUTO * /MCAS1 * /MCAS2 * / /MWE * /ROM-OE ( Wait until CAS in hard disk read ) / /MRAS = HI ( Tri-State enable ) + / /MREQ * /RAS-INH * /ROM-OE ( RAM acces ) + / /MREQ * / /HIGH-ROM * / A15 * / /ROM-ENB * /ROM-OE * / AUTO * / /READ + / /MREQ * / /HIGH-ROM * / A15 * / /ROM-ENB * / /RAS-INH * / AUTO * / /READ ( Normal ROM access ) + / /MREQ * / /MRAS * / /READ * AUTO * / /READ-SYNC * /ROM-OE + / /MREQ * / /MRAS * / /READ * AUTO * / /READ-SYNC * / /RAS-INH ( ROM access during hard disk I/O ) / /RAS-INH = / /MCAS1 * / /MREQ + / /MCAS2 * / /MREQ ( Normal RAM cycles ) + / /MREQ * / /HIGH-ROM * / A15 * / /ROM-ENB * MUX * /ROM-OE * / AUTO * / /READ + / /MREQ * / /MRAS * / /READ * AUTO * / /READ-SYNC * MUX * /ROM-OE ( ROM cycles ) / /MCAS1 = / /MREQ * MUX * / AUTO * / /READ * / BANK2 * / /HIGH-ROM * / A15 * /ROM-ENB ( RAM bank1 low bank read ) + / /MREQ * MUX * / AUTO * / /READ * / BANK2 * /HIGH-ROM ( RAM bank1 mid bank read ) + / /MREQ * MUX * / AUTO * / /HIGH-ROM * A15 ( RAM bank1 high bank read or write ) + / /MREQ * MUX * / AUTO * /READ * / BANK2 * / XFER ( RAM bank1 normal write ) + / /MREQ * MUX * / AUTO * /READ * BANK2 * XFER ( RAM bank1 xfer write ) + / /MREQ * / /MCAS1 * / AUTO ( Latch until MREQ goes away ) + / /MREQ * MUX * AUTO * /MWE * /READY ( RAM bank1 read during hard disk I/O ) + / /MREQ * MUX * AUTO * / /MWE * / /READY * / /WAIT ( RAM bank1 write during hard disk I/O ) / /MCAS2 = / /MREQ * MUX * / AUTO * / /READ * BANK2 * / /HIGH-ROM * / A15 * /ROM-ENB ( RAM bank2 low bank read ) + / /MREQ * MUX * / AUTO * / /READ * BANK2 * /HIGH-ROM ( RAM bank2 mid bank read ) + / /MREQ * MUX * / AUTO * /READ * / /HIGH-ROM * / A15 * BANK2 * / XFER ( RAM bank2 low bank normal write ) + / /MREQ * MUX * / AUTO * /READ * /HIGH-ROM * BANK2 * / XFER ( RAM bank2 mid bank normal write ) + / /MREQ * MUX * / AUTO * /READ * / /HIGH-ROM * / A15 * / BANK2 * XFER ( RAM bank2 low bank xfer write ) + / /MREQ * MUX * / AUTO * /READ * /HIGH-ROM * / BANK2 * XFER ( RAM bank2 mid bank xfer write ) + / /MREQ * / /MCAS2 * / AUTO ( Latch until MREQ goes away ) PAL. END Wheî thå machinå poweró up¬ RESEÔ wilì cleaò thå BANË registeò selectinç ROÍ anä clearinç AUTO-ENA® Thió placeó thå disë hardwarå iî floppù modå iî whicè thå clocë runó continuously® Aô thå enä oæ thå currenô bytå time¬ statå wilì loaä froí eitheò thå latcè oò thå prom¬ neitheò oæ whicè arå initialized. Therå haó beeî somå discussioî regardinç thå disablinç oæ thå Šdrivå decodeò afteò motoò timeouô tï turî ofæ thå activitù light® Iæ thå motoò resetó tï off¬ nï driveó arå selected® Assertioî oæ write-gatå (thå onlù baä newó resulô oæ noô initializinç thå statå register© woulä havå nï effect. Iæ AUTO-ENÁ werå set¬ AUTÏ inactivå woulä cleaò thå statå registeò selectinç thå latch® Thå latcè coulä theî bå seô tï null® Wheî AUTO-ENÁ ió cleared¬ thå statå registeò woulä reloaä itó nulì aô thå enä oæ eacè bytå time® 4/29/83 Swapped 15 and 23. 5/11/83 Removed superfluous terms from both mcas outputs. Added /READ-SYNC to mcas1. 5/13/83 Latched RAS-INH during MREQ 9/1/83 Removed RAS-INH latch during MREQ. Removed AUTO-ENA input and /MODE-CLR output. Added XFER and A15 inputs. Renamed MS0 to /ROM-ENB. Renamed MS1 to BANK2. Renamed /HIGH to /HIGH-ROM. Revised all output equations to add interbank xfer, and change memory map scheme. 9/10/83 Added MRAS to ROM acces terms in MRAS and RAS-INH during READ-SYNC. Replaced DSR1 with MWE everywhere except MWE. 1/31/84 Qualified two ROM terms with MUX to prevent glitching and latching on first AUTO cycle if MREQ comes before WAIT.