[1771.PCB] [macro collection to generate WD-1771 disk controller board] [directory] <00010203040506070809101112> [hztl 14 pin] <00=6(v5eue)v17nun6(v5wuw)v17susv;> [hztl 16 pin] <01=7(v5eue)v17nun7(v5wuw)v17susv;> [hztl 20 pin] <02=9(v5eue)v17nun9(v5wuw)v17susv;> [hztl 24 pin] <03=11(v5eue)v35nun11(v5wuw)v35susv;> [vtcl link 1] <04=uevwuwveu18s3d21s3c2svs;> [vtcl link 2] <05=uevwuwveu6s3c21s3d14svs;> [memory org] <06=o40s8e;> [mem sectn] <07=6m4(3m48s)6m36n3(12(4m48n6e)72w48s) 6m3(12(5m48n6e)72w48s);> [addr latch] <08=o22s92e;> [addr sctn] <09=8m2m;> [adr bottom] <10=8m2m 12eu2b94wv 2n6eu98e3dvd 12eu6b102wv 2n6eu106e7dvd 18n6eu8c106wv 2n6eu90e5ava 12wu4c76wv 2n6eu60eava ;> [counter org] <11=o52s92e;> [counter sec] <12=11m4(1m30s)11m72e30n4(1m30s);>