40 Pin Expansion Connector
The Model 1 has a 40 pin bus connector on the left rear of the case, which
allows connecting various peripherals. It is mainly used for the Expansion
Interface, a box containing an additional 16 or 32K of RAM, a floppy disk
controller, a printer port, and possibly an RS-232 port.
The expansion bus pinout is as follows:
Pin (hex) |
Sig Name |
Description |
1 |
RAS* |
Row Address Strobe output for 16 pin dynamic rams |
2 |
SYSRES* |
System reset output. Low during power-up initialize or when the
reset button is pressed |
3 |
CAS* |
Column Address Strobe output for 16 pin dynamic rams |
4 |
A10 |
Address output |
5 |
A12 |
Address output |
6 |
A13 |
Address output |
7 |
A15 |
Address output |
8 |
GND |
Signal Ground |
9 |
A11 |
Address output |
10 |
A14 |
Address output |
11 |
A8 |
Address output |
12 |
OUT* |
Peripheral Write strobe output |
13 |
WR* |
Memory Write strobe output |
14 |
INTAK* |
Interrupt Acknowledge output |
15 |
RD* |
Memory Read strobe output |
16 |
MUX |
Multiplexer Control output for 16 pin dynamic RAMs |
17 |
A9 |
Address output |
18 |
D4 |
Bidirectional data bus |
19 |
IN* |
Peripheral Read strobe output |
20 |
D7 |
Bidirectional data bus |
21 |
INT* |
Interrupt input (Maskable) |
22 |
D1 |
Bidirectional data bus |
23 |
TEST* |
A logic 0 on TEST* input tri-states A0-A15, D0-D7, WR*, RD*, IN*, OUT*, RAS*, CAS* and MUX*. |
24 |
D6 |
Bidirectional data bus |
25 |
A0 |
Address output |
26 |
D3 |
Bidirectional data bus |
27 |
A1 |
Address output |
28 |
D5 |
Bidirectional data bus |
29 |
GND |
Signal ground |
30 |
D0 |
Bidirectional data bus |
31 |
A4 |
Address output |
32 |
D2 |
Bidirectional data bus |
33 |
WAIT* |
Processor wait input, to allow for slow memory |
34 |
A3 |
Address output |
35 |
A5 |
Address output |
36 |
A7 |
Address output |
37 |
GND |
Signal ground |
38 |
A6 |
Address output |
39 |
+5V |
(limited current - Level I Model 1s only) |
40 |
A2 |
Address output |
Expansion Bus Card Edge Connector as viewed
from the rear of the computer.
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
-#--#--#--#--#--#--#--#--#--#--#--#--#--#--#--#--#--#--#--#-
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
Explanation of Expansion Bus signals
Address Output:
There are 16 address lines, labeled A0 through A15.
A0 is the least significant bit, while A15 is the most significant bit.
These lines are the address bus from the Z80 microprocessor. Each line
is capable of driving ONE standard TTL load.
Bi-directional Data Bus
These eight lines, D0 through D7, are what the
CPU uses to move data from one part of the computer
to another. D0 is the least significant bit, while
D7 is the most significant.
Row Address Strobe output
The RAS* line goes low when the CPU is outputting the
row portion of an address. Used for accessing
dynamic RAM.
Column Address Strobe output
The CAS* line goes low when the CPU is outputting the
column portion of an address. Used for accessing
dynamic RAM.
Multiplexer Control output
The MUX output is used to select the proper address line
in conjunction with RAS* and CAS* for accessing the RAM.
System Reset output
The SYSRES* output goes low only when the RESET button is
pressed, or when the computer is first powered up. This can
be used to reset an external device at the same time the TRS-80
is reset.
Test input
When the TEST* line is taken low, the data, address and control
group buffers will tri-state. That is, they will be disconnected
from the rest of the world. This is normally only used during
factory testing or during troubleshooting.
Processor Wait
When taken low, WAIT* will pause the CPU from firther processing
until WAIT* goes back high. In some cases, an external device will
need additional time to send data to the processor. The WAIT* input
allows the external device to take the time it needs.
Memory Write strobe
When *WR goes low, the CPU is writing the data present on
the data bus to the memory location specified by the
address bus.
Memory Read strobe
When *RD goes low, the CPU is reading data present on
the data bus from the memory location specified by the
address bus.
Peripheral Write strobe
OUT* operates like WR*, except that it is for port output
instead of memory write. When OUT* goes low, the CPU is
trying to send the 8 bit data on the data bus to the I/O
port specified by the 8 low order bits of the address bus (A0
through A7). The Model 1 can address up to 256 output ports.
Peripheral Read strobe
IN* operates much like RD*, except it is for input ports instead
of RAM memory. When IN* goes low, the CPU is looking for data at
the port address specified by the low 8 bits (A0-A7)
of the address bus. The Model 1 can address up to 256
input ports.
Interrupt input
INT*, when taken low, will force the CPU to a predetermined address in
the computer's ROM. Although the Z80 CPU allows several interrupt modes,
there is only one available on the TRS-80, the jump to 0038H.
Interrupt Acknowledge
INTAK* goes low whenever the the CPU enters an interrupt mode.
Signal Ground
This is the reference point for all voltages and logic levels in the Model 1.
+5 volt output
This line is at +5V only on Level 1 Model 1s. On Level II machines, this pin
has been modified to be GROUND.
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