That pesky Jupiter Ace *still* won't work...t

[Tony Duell]

> In message <m19MYT7-000IzSC at p850ug1>
>           ard at p850ug1.demon.co.uk (Tony Duell) wrote:
> 
> > You have a 'scope, and the outputs of the timing chain should be pretty 
> > regular, so it's not hard to ensure it's clocking correctly... You have 
> > checked the CPU clock, etc, are presnet, right?
> I can't see why the timing chain could be at fault. The master clock (for the
> Z80) is running, the sync signals (which require pretty much ALL of the
> signals from the TIC to be working) are OK...

Sounds as though the timing chain is fine, but it can't hurt to check it.

IIRC there's some kind of multiplexer between the timing chain and the 
video RAM address lines (I can't remember if this is a real mux, or one 
of the Jupiter Ace type ones [1]). Maybe worth checking that's OK.

In fact have you checked you have some activity at all the address and 
data pins of all the RAMs? If you see a pin that looks 'stuck' it would 
be worth investigating.

[1] A vile idea of putting a 1k resistor in series with a TTL output and 
then coupling it to a 3-state output. If the 3-state output is 'off' then 
the other (totem-pole) output drives the line via the 1k resistor. If the 
3-state output is 'on', then it overrides the signal coming via the 1k 
resistor...

> > You mentioned earlier that the ACE only loads the chargen after checking 
> > program RAM, etc. What does it do if the test fails? HALT? Goes into a 
> > tight loop? Can you see if it's getting there with the 'scope (if it's a 
> > tight loop, most of the address pins should be static, at least during 
> > MREQ cycles).
> It looks like I misunderstood the code - it stores 0xFC in every byte,
> starting from the bottom of the main RAM, until the byte it reads back is not
> equal to 0xFC. It then rounds the RAM count down to the nearest kilobyte.

Right. What does it do if it finds no valid RAM?

> Obviously, if it thinks the RAM isn't set up right, the stack is going to get
> pretty badly fudged. That shouldn't stop it from loading the CHG though...

Are you sure no stack or data memory is needed for this...

> My money's on a short circuit somewhere in the VRAM circuitry.

For it to load the chargen, the Wr/ and CS/ signals to the chargen RAM 
must be asseted at the same time, right? Can you attempt to detect this 
with the 'scop, maybe with an external OR (or NOR) gate? If you can 
trigger on that [2]  (assuming a good 'scope [3]), then maybe you can 
look at the data going into the chargen, etc.

[2] A useful trick, I don't rememebr where I learnt it, is to pulse the 
reset line at a few 10's of Hz. Slow enough that the machine does 
something after each reset, but fast enough that you get repetitive 
signals to look at on the non-storage 'scope.

[3] A delayed timebase is very useful here....

-tony