6800 opcode $02
jcwren at jcwren.com
Tue Aug 30 20:45:00 CDT 2005
I'd suggest finding a VHDL or Verilog implementation, and see if
that provides any insight. Also, Google for '6800 undocumented opcodes'
(no quotes). There are a number of hits. Most seem to indicate that
the undocumented opcode (no value given) causes the processor to go into
a mode where there are no instruction fetchs, but the address bus runs
incrementing bus cycles.
Scott Stevens wrote:
>On Mon, 29 Aug 2005 17:53:59 +0100 (BST)
>ard at p850ug1.demon.co.uk (Tony Duell) wrote:
>>Does anyone know what Opcode $02 is on a Motorola 6800 processor. It's
>>not defined in the data sheet, but I have a device which forces that
>>instruction onto the data bus in one of the test modes.
>>Is it, by any chance, the infamous HCF instruction?
>Hmm, all the other $0x opcodes on the table are inherent instructions
>that mess with the condition code register. Looking at the order of the
>bits in the instructions, I don't see an order that corresponds with
>good old HINZVC (we were required to memorize this, the order of the
>bits in the condition code register, in tech school)
>0a clears overflow (V)
>0b sets overflow (V)
>0c clears carry (C)
>0d sets carry (C)
>0e clears interrupt mask (I)
>0f sets interrupt mask (I)
>The lower instructions defined are
>06 Accumulator A to CCR
>07 CCR to Accumulator A
>Is there a bit-level 'Opcode Breakdown' reference for the 6800
>processor, that defines bit field and gives clues to how the opcodes are
>translated in hardware, like there is (it's an elaborate table and I
>even have a machine language Textbook that drags you through it all on
>an early chapter) for the 8086 processor?
>The good old 6800. 'Freescale' : bah!
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