PDP-8 CPU question

Tony Duell ard at p850ug1.demon.co.uk
Sat Jun 18 18:16:43 CDT 2005

> I think in this case, the JSR/ROM issue is moot... doesn't the M8317
> 'toggle' the boot into low core?  I didn't think M8317 PROMs were
> memory mapped.

If that's the diode matrix boot ROM then yes it does. The 'SW' switch on 
the panel starts the process, the ROM board then acts like a front panel 
(does the same things to the Omnibus signals) to copy the bootstrap into 
core. IIRC one of the rows of diodes defines the start address (the board 
effectively does a load-address operation with those diodes acting like 
the panel switches).

There was another ROM/RAM board that was typically used to store user 
software, not bootstraps. That does appear in the normal memory map. IIRC 
there are 13 bits per location. The 13th bit is a flag, if it's in one 
state, then the data is read from the EPROMs (1702s, of course). If it's 
in the other state, then 8 (IIRC) of the EPROM data bits are used as an 
address into a 256 location RAM, and the contents of that RAM location 
are fed to/from the bus. This means you can do the normal subroutine 
link, etc.


More information about the cctalk mailing list