PDP-8 /e/f/m memory

[Allison]

>
>Subject: Re: PDP-8 /e/f/m memory
>   From: "vrs" <vrs at msn.com>
>   Date: Mon, 14 Aug 2006 00:04:38 -0700
>     To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org>
>
>> Even schematics would help.  In the end I may do my own as 
>> a pair of 61256s will certainly fit the bill and barely fill
>> a corner of a board.
>
>I looked at doing one of these, but got kind of lost about how 
>the timing signals are used.  I looked at the MOS RAM for the 8/A, 
>but there's all this cruft for refresh in there, some stuff about 
>suppressing access during ROM access, etc.  And then it looks like 
>the memory timing signals are derived somehow from the memory 
>refresh stuff??
>
>Is there a nice place where the Omnibus memory interface control 
>signals are explained somewhere?

Small Computer Handbook 1973 is a good staring point.  A complete prinset
also has details like timing.  



Allison