Original 11/74 front panel

[Johnny Billquist]

Don North <ak6dn at mindspring.com> wrote:

Johnny Billquist wrote:

 >>> "Julian Wolfe (FireflyST)" <fireflyst at earthlink.net> wrote:
 >>>
 >>
 >>>>> Okay, what I immediately noticed is that these machines say "MP" and
 >>>>> Don's panel doesn't.
 >>
 >>> More differences: Don's panel have the location for the key moved to
 >>> the other side of the parity lamps. Which is rather weird.
 >>> Also, the screenprint of 11/74 looks shadowed, which is weird. And the
 >>> right hand side have a different color than the left hand side.
 >>> And of course, the 11/74s from Tim don't have any CIS stuff on the
 >>> front panel.
 >
 > Besides moving the keyswitch, the dial selector knobs on the righthand
 > side were moved around as well to make space to label all the extra
 > switch positions.
 >
 > As I mentioned in another reply, the artifacts are due to scanning the
 > panel on a 14" flatbed scanner in two pieces, and merging the scans.
 > When I get around to it I'll take a high quality single-view photograph.

Yes, I saw that.
Well, that explains those artifacts. It would definitely by nice if you 
could take a good photo of it at some time.

 >>> (I'm still thinking that Don's panel have never had a matching piece
 >>> of real hardware, since I don't think that CPU was ever built.)
 >
 > I can only say that I worked on real 11/74 hardware in 1978-9 writing
 > microcode for the 11/74 CIS (commercial instruction set) accelerator
 > (packed decimal, string instructions, etc). See
http://www.bitsavers.org/pdf/dec/pdp11/1174/Prelim_KB11-E_Diffs_Aug78.pdf
 > for a memo written by Ray Boucher, one of the hardware designers (Al,
 > how did you ever come across a memo such as this???). The other hardware
 > designed was Mike Brown. The other microcoders were Dave Sager and Lewis
 > Costas. The project manager was Dave Barry. How much more do you need to
 > know?

Ok. I'm conviced. :-)
Thanks, by the way for clearing that up.

 > Not a lot of 11/74 CIS systems were built, probably no more than a dozen
 > or so maximum. The 11/74 folded in the 11/70MP changes which had been
 > done about a year earlier, so an 11/74 was really an 11/70MP base plus
 > the CIS option. Later when the 11/74 CIS was killed as a product, the
 > 11/74 name lived on, but it was strictly a renamed version of the 
11/70MP.

Wonderful that some were really built. Were they every used for 
anything, or were they just built to prove it worked, and then 
cancelled? What happened to those machines?

Hmm, you raised a new question in my mind. I have always been under the 
impression that the 11/74 designation was for the MP system, but here 
you seem to imply that the 11/74 was really the 11/70 with CIS, and the 
moniker was actually only taken over by the MP system after the 11/70 
CIS was cancelled. Is that correctly understood? If so, that's interesting.

Do you know why they cancelled it? (Well, I could guess that the CIS 
really didn't turn out to be something customers asked for, especially 
not after the VAX started rolling, but anyway...)

 >>>>> Were there non-multiprocessor 11/74s?  If so, what would have been
 >>>>> the benefits over 11/70s?
 >>
 >>>
 >>> Yes there were. And the benifits were none. Actually, they were
 >>> slightly worse than normal 11/70s, but the difference were minimal.
 >>> After DEC decided to not make the 11/74 into a commercial product,
 >>> they used 11/74 parts for 11/70 machines. Atleast inhouse. Not sure if
 >>> any of those parts found their way into customers machines.
 >>>
 >>> Used as such, the differences were basically related to cache: The MMU
 >>> have the cache bypass bit. The ASRB instruction always bypass the
 >>> cache, and you can also order the machine to explicitly bypass the
 >>> cache (unless my memory fails me).
 >>>
 >>> But nothing of this was used by any OS normally, so the only thing
 >>> noticeable would be the slower ASRB instruction.
 >>>
 >
 > All true statements. ASRB to memory was modified to act as the semaphore
 > instruction and thus always bypassed the cache AND did an atomic
 > read/modify/write cycle to the memory. The valid semaphore memory values
 > were 0 and 1; ASRB would then always set the memory value to 0 and
 > return the old value in the C-bit from the right shift carry out.

Just to clarify things here. The ASRB didn't always write a 0 back, it's 
just for the spinlock semaphores that only held the value 0 or 1 that 
ASRB in effect always wrote a 0 (right?).
I seem to remember some other paper about this that also pointed out 
that one optimization done was that if the data read by the ASRB was 
already 0, it didn't do a write at all, which improved efficiency a lot.

Thanks for providing some insight here. If you have more gems stored in 
your head, perhaps we could talk a bit offline. There are things I'd 
like to know. :-)

	Johnny

-- 
Johnny Billquist                  || "I'm on a bus
                                   ||  on a psychedelic trip
email: bqt at update.uu.se           ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol