Home written editors (was Re: Where to buy a Selectric?)
jos.mar at bluewin.ch
Mon Jan 2 01:29:35 CST 2006
> Verilog isn't too hard if you already know C. VHDL is Pure Evil (tm)...
Not in my book that is....
Verilog is severly lacking in basic areas : in my mixed mode (analog /
digital ) simulations I use "std_logic" for digital signals and "real"
for analog signals, bias currents, ref. voltages etc. We also use
different types for the different voltages domains in a chip.
In VHDL this makes an excellent combination.
Verilog just cannot handle this at all. It is suited for simple digital
But since, in future, all designs will be done in System-C, only
seasoned C++ progammers will be able to do hardware design....
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