Philip Freidin wrote: > On Sat, 31 Dec 2005 16:48:14 -0700, you wrote: > > There is nothing about the logic fabric of FPGAs that has a bias for 4 bits. > You can build (and I have) arithmetic data paths of any bit width, even 17 > if it makes sense. Sorry to disagree here. The LUTs are 4 bit wide, so working with 1..4 bits causes the same delay.