Homebuilt TTL and transistor CPUs

[Roy J. Tellason]

On Wednesday 04 January 2006 06:16 pm, Dwight Elvey wrote:
> From: "Roy J. Tellason" <rtellason at blazenet.net>
>
> >On Wednesday 04 January 2006 09:31 am, J.C. Wren wrote:
> >>     This fellow has some interesting projects.  A 6502 opcode compatible
> >> CPU implemented in latches and EEPROMs.  A NAND-gate based MC14500B.
> >> And a CPU using (mostly) only transistors.  Also a introduction to
> >> microprogramming article, and some other good stuff.
> >>
> >>     <URL: http://people.freenet.de/dieter.02/index.htm >
> >>
> >>     I don't know if anyone else mentioned this page in the past.  I
> >> don't recall it, and I tend to follow the homebuilt CPU threads here.
> >> If you've seen it already, sorry about that.
> >
> >I wonder how fast you could get one of those to go...?
> >
> >--
> >Member of the toughest, meanest, deadliest, most unrelenting -- and
> >ablest -- form of life in this section of space,  a critter that can
> >be killed but can't be tamed.  --Robert A. Heinlein, "The Puppet Masters"
> >-
> >Information is more dangerous than cannon to a society ruled by lies.
> > --James M Dakin
>
> Hi
>  I suspect the limits are bus and speed of the EEPROM's. One
> can get EPROMs that are in the 50 to 60 ns someplace but
> getting data from normal random access memory can be
> an issue. Using one of the newer protocols, such as DDR
> would require a memory interface that was almost as complicated
> as the uP you were building.

You're probably right,  but I don't think I'd want to go there anyhow.  
Considering the seriously low speed of some of those early 8-bit parts it 
wouldn't be at all hard to improve on it.  Heck,  I know of a lot of people 
that went to some nontrivial effort to do things like upgrade a stock Kaypro, 
and I remember thinking how nifty it'd be when I first heard about a 20 MHz 
z80 coming out.  And with simple programs and efficient design you could get 
some good results out of such a setup.

>  Still, there are a number of processor models that make sense
> for using slower memory. I've seen one that used a 20 bit data
> bus and most instructions were 5 bits. This means that 5 operations
> can be done on one instruction fetch. This doesn't work well
> with the typical RISC machine because you need operands.
> It does work with zero operand machines quite nicely :)

Yep,   I imagine it would.  :-)

-- 
Member of the toughest, meanest, deadliest, most unrelenting -- and
ablest -- form of life in this section of space,  a critter that can
be killed but can't be tamed.  --Robert A. Heinlein, "The Puppet Masters"
-
Information is more dangerous than cannon to a society ruled by lies. --James 
M Dakin