Mystery Q-bus boards
henk.gooijen at oce.com
Wed Nov 22 16:01:44 CST 2006
>Ethan Dicks wrote:
>>> Well, on the CompuServe board, there is a 68B09 which is (I believe) an
>>> 8MHz version of the 6809.
>> Hmm... I would have thought that it was a 2MHz part, but some googling
>> does show the B variant clocked at 8MHz. If that's the case, I wonder
>> if it's possible to overclock Henk's "Real Console".
>No, it *is* 2MHz. The confusion is because if you use the on-chip
>oscillator, you use a crystal that's 4x the E clock frequency, so an
>8MHz crystal for a 2MHz clock.
>>> There's a 68B40 which I think is a CTC (counter/timer)...
>> That it is. It's also known as a "PTM" - Programmable Timer Module.
>> Some light digging around seems to show that it's a 2MHz part.
>Yes, though it can use an 8MHz input via the on-board prescaler on one
>Pete Peter Turnbull
> Network Manager
> University of York
I left most of the original message intact.
Yes, you can run the Blinkenlight Core Board (and I/O board) with an 8 MHz
Xtal. The 6809 (B version) will run at 2 MHz, due to the E and Q clock
generation. The 6809 uses a 4 MHz Xtal and one instruction cycle is one
microsec. The 68A09 runs with a 6 MHz Xtal and the cycle is 666 ns. The
68B09 uses an 8 MHz Xtal and the cycle is, you guessed, 500 ns.
The CPU "speed" equal clock frequency divided by 4. I hope I have the
nanosec numbers right.
The pdp8/e simulation runs at best performance, with a 68B09 at 8 MHz.
All parts of the Blinkenlight Board set can handle that frequency.
Also, for my floppy disk interface, to read FAT-12 floppy (DD, not HD)
you really need that speed, otherwise you can not keep up the data rate
the FDC presents the data stream. See my project folder ...
The PTM (6840) has three 16-bit timer/counters IIRC, but you can find that
in any old Motorola handbook.
In a different thread, now on CCtalk (FPGA) is an interesting discussion.
Till now I haven't said much, as I am just starting. Like Vince, I bought
an FPGA from Xess. Actually we bought 4 with 4 people ... I just haven't
had the time to start with my Xess module! There is a core for that FPFA
that simulates a 6809 at 50 MHz, effectively giving an 80 ns cycle time!
That would make the pdp8/e simulation run at the speed of the pdp8/s.
The ultimate will be of course, not to simulate the 6809 in the FPGA,
which in software simulates the pdp8, but let the FPGA simulate the pdp8
right away. With the I/O latches connected to the FPGA you would have
a nice hardware simulation of the 8/e ... Just my thoughts.
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