Stack Machines

[Chuck Guzis]

On 22 Oct 2006 at 20:14, Ray Arachelian wrote:

> The same way one efficiently does large vector arithmetic on a non-stack
> machine.

I'm talking about SIMD implementations here.

    <load R1 with address and length of source vector 1>
    <load R2 with address and length of source vector 2>
    <load R3 with address and length of destination vector 3>
    <load R4 with address of sparse bit vector 1>
    <load R5 with address of sparse bit vector 2>
    <load R6 with adddress of sparse bit vector 3>
    ADDSV	(R1,R4),(R2,R5),(R3,R6)		Add the two sparse vectors

The point being that most vector capabilities are three-address 
implementations--because they run fastest.

Cray went so far as to adopt 3-address architecture using vector 
registers rather than 3-address memory-to-memory operations. 

But no stack vector machines exist to the best of my knowledge, 
although a vector stack would certainly be possible to construct.  
No, what I've seen are your dumb old three-address implementations.

I think that speaks volumes regarding performance.

Cheers,
Chuck