11/34 failing trap test

[Patrick Finnegan]

On Saturday 23 September 2006 05:03, Julian Wolfe wrote:
> On Sep 22, 2006, at 12:16 PM, Don North wrote:
> > Julian Wolfe wrote:
> >> Okay, it halts with 20 in the octal display.  Is that the address?
> >>
> >> I guess I need to take this one step at a time.
> >>
> >> On Sep 20, 2006, at 1:39 AM, Don North wrote:
> >
> > Ok, this means that the halt instruction was at 16(8) and probably
> > came from the trapcatcher setup at 14(8). You can verify this by
> > examining location 14(8) and see that is has a 16(8) in it.
>
> I did that and got exactly as expected.
>
> > 14(8) is the vector for the BPT instruction. Now you need to examine
> > the SP and look on the stack at (SP) to find the saved PC of where
> > the actual trap occurred. This should be back somewhere in the program
> > code (if you are lucky). It could be you are unlucky :-(, your CPU
> > went
> > wild and just happened to run across an instruction word with an
> > opcode of 000003 (which is BPT).
>
> Examining the SP gives me a value of 470(8) on the display. Now, from
> what I understand, I should be looking for this address in the
> listing, correct?

No, SP (which I take it has the value of 470(8)) is the stack pointer, so you 
should look at the contents of address 470(8) to find out the value of PC 
when the machine trapped.  The notation (SP) means the contents of the 
address indicated by SP.

Now, most machines I've used decrement SP *after* storing the value -- which 
would mean that the PC should actually be stored at 472(8).  Is the PDP-11 
different, or should Julian actually be looking at 472(8) instead of 470(8)?

Pat
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