TTL 7400's Available

[woodelf]

Brent Hilpert wrote:

> Because the slave section outputs are all modified simultaneously,
> but asynchronous to the master sections, the master section inputs are
> guaranteed to be stable when the master sections are gated (as long as the
> longest logic propagation path is accounted for).
> 
>  Advantages:
>   - simple flip-flop design, no need for edge-triggerring.
>   - no concern about setup or hold times.
>   - fully synchronous at the system level, no worrying about
>     propagation glitches, etc.
> 
>  Disadvantages:
>   - every 'system flip-flop' or 'bit of state' is actually two (gated) flip-flops.

That is what I plan to use -- the problem is generating the two phase clock.
Q: How to do that.
> (Another cheap trick in the SSI IC era was to front a basic 2-gate flip-flop
> with discrete capacitors and resistors to get edge triggerring.)

A: See above.
> .