Emulating old computers on FPGA
bfranchuk at jetnet.ab.ca
Wed Jun 20 21:47:35 CDT 2007
Alexandre Souza wrote:
>> E) *** Watch out for routing problems problems ***
> But how can I spot that?? Are you talking about routing inside the
Yes. But the only way to find out is to build your design.
>> You can only get about 70% to 80% of the logic
>> in CPLD used before you need to go to a bigger chip.
Or you run in to pin locking problems.
This where a design is sensitive to the I/O pin assignments
used. Pins assigned A B C D may not work, but pins assigned
B D C A might.Or you assign pins A B C D and the router desides
to re-order it as B C A D.
>> F) Your CAD/PCB programs can handle any weird pin out
>> often need by new chips ... they don't make CPLD's in
>> 16 pin dips. :) That is that last reason I am not using
>> CPLD's , I need a 84 pin PLCC socket with my PCB program.
> Diptrace is a good program, take a look at that! ;o)
I gone to using 2901's and LS TTL. I still have a few more
things to design until I am ready for a $$$ PCB program.
More information about the cctalk