(another) Floppy disc reader status update and RFC

[Philip Pemberton]

Hi guys,
   Progress is going a little slower than I'd hoped.. I've been roped into 
working most of the past few weeks, so all I've got done is the final block 
diagram and part of the schematic.

   What I have got is a box containing £200 worth of CPLDs, Molex connectors, 
and other parts I had to order from Digikey. What this basically means is that 
after I've got the schematic and PCB done, I can get a prototype built up 
within a day or so of finishing the PCB. Assuming, that is, I manage to etch 
the PCB without any bridged/broken tracks (especially on the CPLD and PIC, 
which are both QFP parts).

So here's the final spec as I see it:
   - USB interface -- USB2.0 Full Speed (12Mbit/sec)

   - 40-pin disc interface connector. All outputs are open-collector -- the 
first 34 pins are wired exactly as the standard PC floppy connector is. The 
remaining 6 pins are all open-collector outputs with internal 680R pull-ups to 
+5V. The state of these pins can also be read back in, assuming they're set to 
'output high' mode.

   - Replaceable bus drivers. 74LS07 O/C buffers are used - these are not 
generally ESD sensitive, and are rated to 20V over the outputs. All the 
buffers will be socketed and can be replaced easily in the field (as long as 
you have spares, that is).

   - Flexible triggering options:
     - Start of capture:
       - MFM sync word detection, with programmable sync word (*)
       - Rising or falling edge of index pulse
       - Hard-sector track mark detection
       - "Wait for N start events before triggering" option
     - Termination of capture:
       - MFM sync word detection, with programmable sync word (*)
       - Rising or falling edge of index pulse
       - Hard-sector track mark detection
       - "Wait for N start events before triggering" option

(*): The capture CPLD only has one MFM sync detector, which is shared between 
the Start and Stop events. Note that the acquisition clock divider must be set 
correctly in order for the sync word detector to function.

[ A future version of the CPLD may offer the option of independent clock 
generators for the sync detector and acquisition system - currently Facq is 
locked at 32 times the disc's bit-rate, e.g. 500kbit * 32 = 16MHz for 3.5-inch 
HD. This is a fairly simple mod, so I might do it before release, but 32*Fdata 
should be enough to get a usable scan ]

   - 128 kilobytes onboard high-speed SRAM buffer with end-of-capture-address 
storage.

   - Disc writes controlled by a simple microsequencer - commands are:
     - Wait N cycles and strobe WR_DATA
     - Stop writing
     - Open/close Write Gate
     - Wait for hard-sector track mark
     - Wait for N index pulses (where 1 <= N <= 31)

   - Onboard flash upgrading feature for both the main microcontroller and 
CPLD, with failed-flash recovery and forced-reflash options for both devices 
(as long as the bootloader is still intact). The boot block will also be 
protected against overwriting, to reduce the possibility of irrecoverable 
'bricking'.

   - Multi-platform (Linux and Windows initially, OSX if someone ports it) 
programming library to handle disc read/write operations, including full 
source code and example 'dartutil' application.

   - Open-source hardware design, but with hardware available for purchase 
either fully-assembled or as a complete or partial kit (optionally with SMD 
parts soldered down).

   - Power supply: USB bus power or external 7-12V power supply unit.

Can anyone think of anything else before I start drawing up the schematics?

I'm also thinking about an extension to the ImageDisk file format to allow 
storage of raw MFM data, though I'm not sure how to go about doing this... 
creating a whole new format may be a better idea.

So to recap, this is done:
   - Block diagram and outline design
   - CPLD code (all major functional units tested and working)

And this needs doing:
   - Schematics
   - PCB layout
   - Prototyping

I'm currently toying with the idea of moving the half-done schematic from 
OrCAD/SDT to KiCAD [<www.kicad-eda.org>] (on the basis that KiCAD is 
open-source, newer, and can do just about everything OrCAD can do), though 
I've not decided yet. Other suggestions (please don't suggest EAGLE...) will 
be given due consideration :)

-- 
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