Report on vintage "Programmer Electronnic Control" alias "RAF Tornado Computer"
roger.holmes at microspot.co.uk
Sun Mar 11 08:44:49 CDT 2007
>> Then I looked at the pictures, and saw it was made by my old
>> employers, Marconi Avionics who took over Elliott Brothers, and
>> continued to make 920 series machines. I think there were 12 bit
>> versions made by one of the divisions, though I am surprised they
>> were still making them in the 1980s.
> Yes, the unit was made after 1986 I think. One quy in the
> rec.aviation.military claimed, that the box might be from
> early tornados as I mentioned in my original posting. I do
> not know how long development of such an aircraft takes but
> the first take-off was in 1974 I think, so this would match
> the design of this box wuite well - what do you think?
Aircraft development takes a long long time. To make it worthwhile
the aircraft has a long service life. Whilst the computers are bullet
proof in an office/home, the temperature extremes, vibration, high G
forces etc in service means that many failures occur and PCBs could
be replaced many times over the years, so do not pay too much notice
of the dates on components of the boards currently installed.
There were at least four 12 bit versions, and one 13 bit apparently.
Then 12 bit models were the 902, 102C, ARCH 105 and Minim or 12/12.
>> One part of Elliott Brothers became GEC Computers (based in
> Yes, that matches - the core memory module already has the
> label GEC. So this is (as I suspected) older than the CPU and
> taken maybe from a different design?!
You have it the wrong way around. The GEC name replaced the Marconi
name, which had earlier replaced Elliott. Core memory was very
convenient for military applications and was in use long after it was
replaced in commercial applications. Think of a missile or torpedo
held in stock for many years, stick a power plug into it and program
the target, pull out the plug and then launch it. Only then does the
internal power supply come up, the processor boots up and does its
>> One of your labels is from Airborne Displays Division based at the
>> same Rochester site as I worked. This was also part of Marconi
>> Avionics, and the company later changed its name to GEC Avionics. I
>> worked on compilers, linkers and other utility software for the 18
>> bit 920s before moving on to the Zilog Z8001.
> Hey, than you are a valuable expert on these - do you have
> got any source of intormation about the 920s?
Not directly but I may be able to help.
>> Erik, could you tell me if the instruction code is anything like
>> 0 Load B (indexing) register and the Q register (shift extension)
>> 1 Add to accumulator
>> 2 Negate and add to accumulator
>> 3 Store the Q register
>> 4 Load accumulator
>> 5 Store accumulator
>> 6 And to accumulator
>> 7 Jump if zero
>> 8 Jump
>> 9 Jump if negative
> RIGHT - all three jumps are relative ones
On the 18 bit machines these were relative to the start of the 8k
memory module the instruction was in. An interesting modification.
>> 10 Increment
>> 11 Store program counter (for function return)
> SIMILAR - This stores PC and then does a
> table jump
On the 18 bit machines, it actually stored the program counter + 1
and the following instruction was either an 8 or a "/8", i.e. 24.
>> 12 Multiply
> RIGHT, unsigned multiplication
This should multiply the signed accumulator and the signed memory
operand giving a double length result in the A and Q registers.
>> 13 Divide
> HMMM, the command takes very long but the results are
> very strange. I thought it might be some type of
> random number generation by an irreducible polynomal,
> but it is definitively not Divide. Maybe here is something
> different or wrong with the microcode.
This divides a signed DOUBLE LENGTH number in the A and Q registers
by a signed memory operand. IIRC the A register gets the result and
the Q register the remainder.
>> 14 Shift
> In PART: Here exist many subgroups of commands including
> shift left/right. Also the Q as you call it can be transferred
> to Accu and vice versa. There als is a MTA (MoveToAccu as I call it)
> which is a two-word instruction (most others are one-word) and
> transfers the word following this command into Accu. About
> 16 bit patterns have (at least to me now) the same meaning in
> this segment.
Shifting by the entire word length does transfer Q to A or A to Q
(but the data disappears from the source). A load immediate
instruction would have been very handy. There was also a block move
instruction here in the 18 bit machines. Maybe some of the special 15
orders were encoded in the 14 order on the 12 bit machines with only
256 numbers available compared with 8k on the 18 bitters.
>> 15 Input/Output and special (like interrupt return)
> Yes, in part as well. Commands for sending and receiving
> via the serial links I found here.
>> 16 to 31, as above but indexed by B register.
> NOPE - The box is 12-bit and does not have got this block.
> EVERYTHING is done via the index register I as I called it.
Do you mean you cannot turn the B-register modification off?
Does it get cleared automatically somehow?
> # # # ##### ###### # # ##
> # # # # # # # # # #
> ##### # # # # ##### #### # #
> # # # ##### # # # ######
> # # # # # # # # # #
> ####### #### # # ###### # # # #
> the box is a 12-bit version of the Elliot series of Computer.
> Lot of work for rediscovering the instruction set of the 920
> Roger, do you have got any detailed information on these
> you are willing to share with me! I am familar with the above
> mentioned instruction set, but some details are still open and
> perhaps studying the Elliot would help to solve the remaining
I am willing to try.
By the way, there are two 't's in Elliott.
>> In early versions of the 920, the B and Q registers were the same
>> register and it and the program counter were held in memory. There
> In this box the registers are stored in "batteries" of 74xxx flip
> flops on the processor boards.
On the later 920s, the current interrupt levels B register and
sequence control register (i.e. program counter) were held in real
registers but the other interrupt ones were held in memory. There was
extra circuitry to make it so that writing to the current level's B
register address actually got trapped and also modified the real
>> were four levels of interrupt and a set of these registers for each,
>> held in location 0 to 7. The high end of memory held a paper tape
>> bootstrap, in later versions, this was just copied into core when the
>> machine was initialised.
> Interesting. The Programmer Electronic Control starts execution
> at 0x0a0 after reset.
Could it be that there is a value of 0x0A0 at location 0?
> But of course the application was different
> and the operation software was completely loaded via the big plug
> boefore operation.
I suspect the big plug is for the OMP (Operator's Monitor Panel), and
yes the program would be loaded via this once, probably in the
factory or at a maintenance depot, and the machine would probably be
rebooted many times afterwards.
>> If this indeed a military machine, you can be sure the memory was
>> erase by flipping every bit backwards and forwards several hundred
>> times to remove any trace magnetism before it was released from
>> the RAF.
> Yes you are probably right. I thought just in case there are some
> fragements inside it would have been interesting to study them
> in order to learn about the instruction set.
> I am sure the unit supports interrupts (one for each serial
> port (panavia link I think) and maybe there is an additional
> for the timer. This timer has a reload register and
> thus can be programmed to arbitrary intervals (12bit, running
> at 2MHz). But up to now I was not able to read or write it
> nor occured an interrupt. Here studying the Elliot would
> really be inspiring - I am very sure that they reused the
> know how here as well...
The 920 was unusual in that it booted into the highest level
interrupt, level 1, so no interrupts will be serviced until you go
down an interrupt level or two or three.
The 15 order is coded thus:
15 0 to 2047 Input
15 2048 Shift A register left 7 places and OR in a character from the
paper tape reader (via OMP)
15 2052 (IIRC) Wait until character pressed on teletype and read into
A register (via OMP)
15 4096 to 6143 Output
15 6144 Output character to paper tape punch (via OMP)
15 6148 Output character to teletype (via OMP) if I remember correctly
15 7168 Terminate current program level i.e. return from interrupt
15 7169 Test if standardised IIRC, skip the next instruction if the
accumulator is zero or top two bits are different
15 7170 Increment B and skip the next instruction if bottom 13 bits
15 7171 Read the value of the control keys on the OMP
15 7172 Move l.s. 17 bits of A to the m.s. 17 bits of Q. Bottom bit
of Q is zeroed
15 7173 Move m.s. 17 bits of Q to l.s. 17 bits of A. Top bit of A is
15 7174 Move A to B
15 7175 Move B to A
15 7176 Set relative addressing mode
15 7177 Set absolute addressing mode
In relative mode, all addresses are relative to the start of the 8k
block of memory the instruction is in. In absolute mode (the
default), 7,8 and 9 orders are still relative but in all others the
address is absolute, so that only the bottom 8k of memory is
accessible without using B modifiers.
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