ard at p850ug1.demon.co.uk
Wed Mar 14 18:21:03 CDT 2007
> A darlington (Q1) and a zener (D3) later... and my +15v (as well as -15v)
> has returned to the requisite spots on the backplane.
> Thanks a TON for the schematics Christian & Al, extra thanks to Al for the
> entire 11/45 printset!! Oh, and Tony, the description of the power supply
> circuit and test points was most helpfull. Thank you! I understand the
> supply itself, but I'm not sure I understand the control circuits just after
> the darlington that will shut it down.
I've not got the schematic in front of me at the moment (I can get it out
qgain if necessary), but IIRC, that shutdown circuit is quite simple. If
the 'spare' DCLO signal is asserted (low), then Q2 and Q3 turn on, that
effectively shorts out the zener, and reduces the base voltage of the
darlington to close-to-0. That then shuts the supply down, of course.
> The machine now springs to life and passes all the front panel tests I would
> normally do. I did manual store/recall of various patterns in core. "clr pc"
> in loc 0 loops as does "br ." in any location. The box also passes a trap
> catcher program. Lastly, it passes a memory address test (puts the address
> of each memory location in each memory location and then verifies).
> Next I would like a way to test interrupts in this minimal configuration
> (that was where the problem was before, no matter what device interrupted it
> would always trap to the same address). I would assume I have to put
> something like an M7856 in next in order to test this. Sound like a
Do you havea KW11-L line time clock in the system? That's a possible
source of interruots.
But I think you need at least 2 different interrupting devices (a DL11
counts as 2, since the transmitter and receiver sides generate different
vectors). Then you can be sure that not all interrupts go through the
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