aclo dclo (11/45) flustered-ness

[Don North]

Jay West wrote:
> Some documentation showed ACLO and DCLO on row C (some docs show only 
> one of those is present) of an SPC slot. If that is the case, should I 
> not see some wire wrapping on my DD11-K that shows ACLO/DCLO 
> (supposedly on B01F1 and B01F2) getting wrapped to somewhere on row C, 
> and daisychaining to all the SPC slots on that same pin so they can 
> monitor it? I do not see that wire wrap on the DD11-DK.
>
> So someone could just tell me what pin to check, to see if ACLO or 
> DCLO is acting funny around my RX02 controller. But I'd really prefer 
> to understand the bigger picture with it as to all places that 
> originate these two signals, what devices can assert them, and most 
> importantly, how those two signals are routed exactly from power 
> supply to the cpu, to the expansion box (which has it's own 
> ACLO/DCLO), all the way to the final M9312. Then not only could I take 
> the measurement, but better understand what I'm seeing.
>
ACLO_L appears on SPC slot CV1, and standard/MUD slots pin BF1
DCLO_L appears on SPC slot CN1, and standard/MUD slots pin BF2

Since ACLO/DCLO are on the standard unibus in/out AB connections, they will
propagate between boxes. They are both open collector, so can be asserted by
any card at any point (altho most cards will treat them as read-only).

You should be able to monitor them on your M9312 on pins BF1 and BF2.

IIRC ACLO and DCLO should work such that if any box/card sees a power fail
condition, it is essentially broadcast to the whole system over the UNIBUS.