HP integral , 82297a
ard at p850ug1.demon.co.uk
Sat Sep 1 16:48:13 CDT 2007
> I seem to rember that people on this list ( Tony ?) have extended a
> 512K memory expansion for the HP integral.
Alas not me. I've upgraded an HP9816 mainboard from 256K to 1M (and for that
matter an HP42S from 8K ro 32K), but that's all.
However, my Integral came with a 1M memory board which claims to be an
HP82916 (PCB 82916-60001).
> <<was it sufficient to stuff the open places on the PCB ?
No, there will amost certainly be some links to move too. If nothing
else, you need to inclesae the address range the card will respond to,
and change the ID byte so that the card so that the system firmware
knows it's a 1M card and configures its address appropriately. The board I
have could clearly be fitted with 1 or 2 banks of either 64K or 256K bit
DRAMs (all chips have to be the same type). There are many links on the
board, as follows :
W1, W2, W3 set the size of each bank (one link only must be fitted)
W1 : 2 off 64K bnaks (256K bytes)
W2 : 1 bank only (128K bytes or 512K bytes)
W3 : 2 off 256K banks (1M bytes)
W4-W9 (6 links) set the size of address range the card will occupy :
W4 : A17 is 'don't care' in card selection
W5 : A18 is 'don't care' in card selection
W6 : A19 is 'don't care' in card seelction
W7 : A17 matters
W8 : A18 matters
W9 : A19 matters
Allowable settings :
W7, W8, W9 : 128K bytes
W4, W8, W9 : 256K bytes
W4, W5, W9 : 512K bytes
W4, W5, W6 : 1M bytes
W10 : CAS jumper
If 64K chips are used, then U45 ('157 mux) may be omitted, in which case
fit W10 to link CAS/ from U47 (TMS4500) to the CAS logic. If U45 is
fitted, W10 must be out.
W11-W16 : Card ID jumpers
W11 : ID bit 2 = 1
W12 : ID bit 1 = 1
W13 : ID bit 0 = 1
W14 : ID bit 2 = 0
W15 : ID bit 1 = 0
W16 : ID bit 0 = 0
I don't know all legal settings for these jumpers (they are simply read
by the irmware, there's no obvious way to deduce their function from the
schematics). I can tell you that a 1M card has W12, W13, W14 fitted.
The first version of my Integral schematics is on the Australian museum
site. This version is know to have errors (in the address decoder circuit
on logic board A), but I think the RAM PCB diagram is correct.
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