Unknows S-100 System
cclist at sydex.com
Sun Sep 23 00:34:21 CDT 2007
On 22 Sep 2007 at 21:34, dwight elvey wrote:
> I saw someone mention the NSC800. I don't think it was mentioned
> that the NSC800 runs Z80 instructions but has the exact same
> pins and interface as the 8085.
Not the same pinout at all; and some signals have inverted polarity.
What's similar is the timing (so the 8085 peripheral chips work)--and
the multiplexed data/address bus. It has the three "half-INT"
signals, but TRAPs to 0066h, like the Z80 and not 0024H like the
8085. There are no RIM and SIM instructions, and therefore, no
SID/SOD pins. There is also a low-power "sleep" feature.
To control the masking of the half-interrupt pins, since there's no
SIM instruction, there is a mask register located at I/O port 0BBh,
accessed by executing an output instruction--but only when accessing
the port via the indiirect "input/output to (C)" instructions; the
0D3h output and 0DBh input to immediate port function normally,
without accessing the internal register at 0BBh.
I never really considered the Z80 to be faster than the 8085, with
perhaps the exception of the 2-byte jump instructions. For
everything else, the Z80 seemed to be roughly as fast for most
things. But the Z80 was easier to program, particularly with the IX
and IY registers, particularly with the 8-bit displacement. And I
suppose interrupt servicing could be faster for high-priority
interrupts where the alternate register set could be used.
One real pain with the 8085 was the input and output instructions.
No indirection at all; just an immediate-valued port. One of the
engineers set up a peripheral that mapped into 64 I/O locations that
essentially forced us into self-modifying code to plug the port
address into a DBh or D3h instruction. That wasn't too bad normally,
but we had to access the ports during POST, which meant moving the
code to RAM from ROM so we could modify the I/O instructions.
What irritated me was that Intel never documented the additional 8085
instructions, even though they seemed to be present on every version
of the chip Intel (and second sources) ever produced. Because they
weren't "officially" documented, we adopted a policy that they should
not be used to avoid possible future "surprises".
I've got about 20 of the 40-pin DIP NSC800s; 3MHz ones, I believe.
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