IBM 5150 maximum memory?
ard at p850ug1.demon.co.uk
Sat Apr 26 14:58:36 CDT 2008
> Two things come to mind, one of which was recently mentioned. The
> interrupt structure was poor -- using edge triggered interrupts prevents
> sharing an interrupt line. As recall the choice of edge or level
> sensitive interrupts is a matter of software (programming a control
> register in the interrupt controller chip). There was no cost
> associated with doing it one way or the other. Someone just decided
> incorrectly, and once the convention was set, it couldn't be undone.
I thought it saved a tivial amount of TTL logic to use edge-triggered
active high interrupts in the realtime clock/heatbeat circuit -- linking
the 8253 output to the 8259. But it was a tirvial amount of logic in a
machine of that complexity/price...
[Why, Oh why, do people always assume the cheapest solution is the best
and will sell the most units. In my workshop that is _never_ the case]
> Another silly thing is that refresh was controlled by a DMA channel.
> I'm sure it saved a couple chips, but it meant that errant, or
And, indeed, using the 8237 DMA chip with a paging register (and not even
doing that as elegantly as the FTS-88 did, which at least had one paging
register per DMA channel) rather than using the 8089 'I/O processor'.
More information about the cctalk