segmented memory models

[Fred Cisin]

> > You are welcome to pick whatever kind of system that you like. Whether or
> > not it is "brain-damaged" is an issue of whether it performs as intended,
> > NOT whether that is yours or my favorite way of doing it.

On Sat, 2 Aug 2008, Tony Duell wrote:
> No, I disagree with you there.
> To me, if something doesn;t perform as intended/as docuemnted, then it's
> brokem. But if that intention/documentation is, shall we say, silly, then
> it's brain dead (even though it performs according to that documentation).
> A hardware example is the active-high edge-triggered interrupts on the
> ISA bus. The system performs as intended (by the designers), it behaves
> as documetned (in the IBM TechRefs). But IMHO it's still brain-dead in
> that, to save one cheap TTL chip, we had IRQ conflict problems for many
> years...

Ah, a matter of semantics.
They didn't INTEND to have IRQ conflicts, and thought that they could get
away with cutting that corner, possibly through a gross underestimate of
how much use the bus would get.

I consider that to be working "as designed", not "as intended".

But, there is no question that mistakes happen, and that design decision
sure seems to be one.
I also don't understand the reasoning behind the mode switching in the
80286.


Back to the OP, . . .
I don't see the segmented architecture as a mistake, but as a successful
attempt to do something that in the long term may have been of
questionable value.  In the short term, it sure made porting software from
CP/M easy.  Lisa and Mac software took a while to develop, but the PC was
inundated with software immediately.  It seemed like it took longer to
edit and reprint the manuals than to port the software.

Similar to the OP, I've even heard programmers declare it to be a bug that
overflowing an offset register doesn't increment the high nibble of the
segment register!


Were either the 5150 or the 8086 architecture intended to last until 1990?


--
Grumpy Ol' Fred     		cisin at xenosoft.com