segmented memory models

[Patrick Finnegan]

On Sunday 03 August 2008, Jim Brain wrote:
> Tony Duell wrote:
> > And what maces the design worse is that the problem had been
> > considered (and correctly solved) before. On the PDP11, the top
> > part of the address space was used for I/O devices. And it was the
> > top part on all PDP11s, whether they had 16, 18, or 22 bit
> > addressing.
>
> I don't think I would call that a correct design.  It forces all
> programs to treat all IO as relative addresses, since they will move
> as the design moves.  If there are processing penalties for relative
> addressing, you've sealed the programmer's fate.

I'll assume from that comment that you aren't familiar with PDP-11 
addressing.  They are still fixed addresses, they all map to (octal)
160000 through 177777 by default.  The extra bits of address space are 
accessible only by programming the memory mapping hardware in the CPU, 
which can map the I/O page (always the top 8192 bytes of memory) to any 
8k boundry in the logical 64kB memory map.

This requires no relative addressing, since the device can always appear 
at the same location in memory, unless you chose to move it by changing 
the memory map.

And, in case you're worried that hardware had to be adjusted depending 
on what address bus used, it didn't.  The CPU asserts a I/O page line 
on the bus whenever there's an access to the I/O page of address space, 
So, the device only needs to check 12 address lines (memory accesses 
are 16 bites wide) and the I/O page line, regardless of how wide the 
address bus on the CPU is.

Pat
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