segmented memory models

[Jim Brain]

Tony Duell wrote:
> No, not as a single chip (AFAIK). But that doesn't stop somebody building 
> one if they want to.
>
> And AFAIK there is no MMU for the PDP11/20 (the first PDP11 
> implementation). And yet it got the extension of 16 bit program addresses 
> to 18 bit bus address 'correct' ((a) what all other 11's do and (b) what 
> was sensible to do given the fact that I/O devices sit at the top of the 
> address space)/
>   
I'll stand my ground.  The fact that one could build an MMU for the 8086 
is different from requiring one in the design of a PC that used the 
8086.  In fatc, who's to say the 8086 designer expected the computer 
developers to use an MMU?  It's not like they could force them to do so.

> No, I don;t think putting the reset at the top of memory was inherrently 
> silly. It's just that it doesn't seem to have served any real purpose. 
> The problems on the 8080 systems caused by having reset jump to location 
> 0 were really due to the fact that reset jumped to a fixed location, not 
> where that location was. So moving it somewhere else neither helped nor 
> hindered anyone.
>   
I think I made a convincing case in one of my previous posts.  I can see 
clearly that 8080 board designers would have carped quite a bit about 
having to map ROM into $000 for boot and wanted that to go away in the 
next iteration of the board.  Or, perhaps Intel just noticed where 
everyone was going, with RAM at 0, and wanted to help make it easier to 
design in the 8086 (I think this was at a time where Intel's dominance 
of the CPU market was not even on the RADAR, so I suspect they did what 
they could to ensure an easy design in.  To play that car further, by 
the time the 80286 came out (and to use your argument that Intel knew 
the 80286 was a sure thing), they probably didn;t care about it as 
much.  People would use the 80286 because it was the next in the 
lineage, and the x86 was a force to be reckoned with.  So, for the poor 
designer who no doubt raised the issue you describe, I can easily see 
them beaten down by the marketing and management types, saying, don't 
waste silicon on it, we *own* this market!

> And that's where I disagree. The addreess FFFF:0000 can _also_ be 
> interpretted as '16 bytes below the physical top of memory. Given that 
> the reset routine is likely to be in ROM, and given that contiguous RAM 
> is generally a good thing, IMHO it would have been better if the physical 
> address outputted by an 80286 for the first instruction after reset was 
> FFFFF0 (not 0FFFF0). One way to do this would have been similar to the 
> PDP11 I/O address trick (which is why I brought that up), namely that in 
> real mode, the 'extra' 4 address lines of the 80286 (over the ones of the 
> 8086) are all set to the same state and that state is the logical AND of 
> the top so-many-bits of the current segment register. 
>   
I really think compatibility concerns trumped the implementation of this 
idea. 

And, even if they truly should have implement the idea you describe, I 
just don't think it qualifies as "brain dead" that they did not.