PDP-8 on FPGA project & where is Hans Pufal?
vrs at msn.com
Thu Dec 18 22:37:48 CST 2008
From: "Philipp Hachtmann"
Sent: Thursday, December 18, 2008 11:08 AM
> Here the entity declaration of my teletype interface, just to give you an
[good stuff elided]
> The break interface is not used by the TTY. I included it just for
> completeness... The wires end open.
> And there's no CLF line yet....
You definitely need the "reset" that the CAF instruction (and the
"clear" key on an 8/e triggers). For an 8/i, it's BINITIALIZE,
which is triggered by the "start" key on the front panel.
> If multiple IO devices are to be connected, the IN lines (to the CPU) must
> be OR'ed together.
The original PDP-8's have these active low, and a logical OR is
implemented with wire-and, via open-collector drivers.
> When my project is in a usable state, I would like to put it on
Cool! It might be an interesting point to work from for what Henk
and I are trying to do.
>> We have Hans' PDP-8 code from a few years ago, and John Kent did some
>> nice work a year or so ago with us to clean up the build and to port to
>> the XESS FPGA card.
> VHDL or Verilog code?
>> I've got the code running FOCAL and other stuff in John's configuration,
>> and the 8/i front panel is pretty much working in that configuration.
> How is it attached? Shift registers?
>> There is currently a regression that broke the IOTs that FOCAL needs, so
>> the more cool code examples don't work at the moment.
> Hm... Which IOTs?
Most of them -- Skips are never skipping, and all IOTs clear AC.
Shouldn't be too hard to fix, but I haven't really looked into
>> and (more importantly) because we don't feel we can redistribute his
> Sure, that he cannot be reached?
Right. The word "license" doesn't appear in any of the files, and
we haven't been able to get a response from him on the subject.
>> I have recently started to implement a "direct coding" of the 8/i
>> schematics in VHDL. That will hopefully give a "clock accurate"
>> implementation of the 8/i.
> What a task!!!
> If you try the real thing, you will get lots of angry warnings about flip
> flop clock input abuse! DEC used the D-flip flops with preset and clear in
> a (today) very uncommon way....!
I'm hoping to get around that by declaring TP1...TP4 (and *strobe*, etc.)
to be the clocks, and re-expressing the latches so that they are clocked
by an "official" clock. I don't know yet how well that is working out,
as it's buried in with the other 188 warnings-of-the-moment.
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