PDP-8 on FPGA project & where is Hans Pufal?

Vincent Slyngstad vrs at msn.com
Thu Dec 18 22:41:41 CST 2008


From: bfranchuk
Sent: Thursday, December 18, 2008 12:20 PM
> Vincent Slyngstad wrote:
>> I'm sure there are other implementations out there.  Maybe some more will 
>> come out of the woodwork :-).
>
> ARGGG!!!!!!
>  **WORMS**

I could only wish :-).

> Check bitsavers for the hardware manuals for the PDP-8 and the PDP-5
> lots of detail in what happens. The problem as I see it is that you are 
> thinking
> the PDP-8 can have any memory thrown at and it works for realistic state 
> emulation.

No, realistic state emulation *requires* every memory cycle to be
read-modify-write (even if you went to the trouble to suppress the
writeback).

> All the computers of that era is based on the  memory cycle of *CORE* 
> memory.
> <setup address><read><pause><write back>   Untill you design your memory
> around that you will have problems. The PDP 8/e's clock was I think 20MHZ
> to generate the proper timing for 1.2us memory cycle, I think you could 
> just get by
> with 5 or 6 clocks per memory cycle. The tricky part is that  Memory 
> buffer register
> is latched with the core data, and then incrimented on the *same* clock.

Yep.

    Vince 




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