PDP-8 on FPGA project & where is Hans Pufal?

[Vincent Slyngstad]

From: "Philipp Hachtmann"
Sent: Friday, December 19, 2008 6:58 AM
>>>>      if (tp4'event and tp4 = '1') then
>>>>         fetch <= f_set;
>>>>         defer <= d_set;
>>>>         execute <= e_set;
>>>>         word_count <= wc_set;
>>>>         current_address <= word_count;
>>>>         break <= b_set;
>>>>      end if;
>>> That's sequential coding!!
>>
>> Not sure what the epithet "sequential coding" means in this context.
>> There is combinatoric logic elsewhere computing the new values for
>> these 6 latches, which take their new values at the beginning of TP4.
>
> Your code above does not result in latches. It results in D type 
> flipflops!
> They're set on the rising edge of tp4.
> You would get latches if you omit the tp4'event part of the conditional 
> expression.

Agreed.  I stand corrected on the terminology.  The part that is being
modeled was originally a 7474 edge triggered device, though, so the
model seems correct.

The real question about correctness would seem to be whether it is safe
to refactor the "gated clock" into the combinatorial inputs.  Which
basically depends, on whether the gating elements are stable by the end
of TSn and throughout TPn.

>> every time I look at the 8/i drawings, they seem more synchronous, so
>> maybe it's just that I haven't fully understood the older machines yet.
> I have my problems understanding the control and sequencing in the old 
> machines.

Me too, though it's generally getting easier.  Basically there are a
mess of delay lines which establish the spacing of the major timing
signals, with a few delay chains that are conditionally inserted for
special (longer) cycles.

    Vince