4.3BSD Quasijarus

Guy Sotomayor ggs at shiresoft.com
Sun Dec 28 19:12:12 CST 2008

There aren't any schematics, but the installation manual is on  
bitsavers.  If I were to do it, I'd look at the cache interface going  
to the MK11 and just build a board that interfaces to that.  Putting  
the memory on with an FPGA to do all of the timing/interfacing  
shouldn't be too hard.  I'm doing something similar for regular Unibus  
memory + ROMs + KW11L + 2 SLUs .  It's basically it's an FRAM, FPGA  
(Spartan 3E), level shifters (3.3v to/from 5v) and Unibus  
transceivers.  All of the work is in the FPGA written in verilog.  It  
shouldn't be hard to do something similar to emulate a full set of  
MK11 memory to the cache interface (probably using high density SRAM  
rather than FRAM).  Depending upon the density of the SRAM(s) it might  
even be possible to do it as a quad board vs hex.  The only thing  
coming from the 11/70 backplane is power and ground (for slot 19).   
All signaling is from the ribbon cables connected to the cache boards  
(4 cables).

TTFN - Guy

On Dec 28, 2008, at 3:50 PM, e.stiebler wrote:

> Guy Sotomayor wrote:
>> The easiest thing to do would be to replicate a PEP-70.  It's  
>> fairly easy as it would be one hex board with all of the memory.   
>> The only modification needed for the 11/70 is 4 power jumpers to  
>> slot 19.  Then just route short cables from the cache boards to the  
>> new board rather than to the external memory boxes.  I wouldn't run  
>> an 11/70 any other way.  :-)
> And the manuals/schematics are where ?

More information about the cctalk mailing list