Pointless question...

[Jim Battle]

Al Kossow wrote:
>  > Suppose one wanted simulate one in modern components.  How would you
>  > do it, if you had, say, a million bits to store?
> 
> Fewest parts would be to use a FIFO feeding the "O" back to the "I"
> 
> I had thought about building a state sequencer this way once for a project
> where the sequence was of programmable length, but didn't require 
> branching.

The recirculation is only part of the problem.  There needs to be logic 
that will accept an address and a datum and will know when is the right 
time to accept this datum instead of recirculating, and will send an ack 
to some other datapath that the write is complete.  Likewise for read, 
it must wait for the right word to come around and then signal when the 
data is finally there.

I think the best approach would be an SRAM and a small FPGA.

If the word was 8b, this would imply a recirc time of 8 Hz, so 
presumably Chuck is thinking of a wider datapath.  In this case, keep 
using an 8b SRAM and clock it at 40 MHz or 80 MHz and mux/demux on the 
fpga to provide a 32b or 64b data port to the outside world.

I'm sure you can buy an FPGA with 1 MB of on-chip SRAM, but it would 
still probably be cheaper to use a small & cheap FPGA and an an external 
SRAM.