Floppy controller Q - VCO Inhibit / VCO Sync, and IBM format

[Allison]

>
>Subject: Floppy controller Q - VCO Inhibit / VCO Sync, and IBM format
>   From: Philip Pemberton <classiccmp at philpem.me.uk>
>   Date: Tue, 29 Jul 2008 20:55:04 +0100
>     To: General Discussion: On-Topic and Off-Topic Posts <cctalk at classiccmp.org>
>
>Hi,
>   I've been playing about with the HDL code for the floppy reader (after a
>"short break") and started thinking about how the VCO Sync/Inhibit line on the
>data separator should be driven.
>
>   At the moment it's driven permanently high; this seems to work OK insofar
>as the sync detector (which is why the datasep is there -- to extract a clock
>signal for the MFM data stream) will pick up SYNC-A1 signals and the data
>seems to be valid. What I don't know is if this is how things are supposed to 
>be done...
>
>   The uPD765 and 827x datasheets are predictably rather sketchy on this 
>front... All they really say is that the VCO line inhibits the VCO in the PLL, 
>which would have the effect of allowing the PLL's loop filter to discharge, 
>and reset it to a predetermined state. What they don't say is under what 
>conditions the FDC will do that...

The VCO is allowed to hold at nominal freq during index gap.  It's in the 
datasheet and a time after index.

The VCO filter should not discharge but insead remain at niminal frequency
rather than seeking phase lock. This is PLL 101.

>
>So I guess the million dollar question is what I should do with said VCO line. 
>Wire it to /INDEX via an inverter to reset the PLL on every rotation? Or just 
>wire it to VCC (VCO enabled) and leave it?

The VCO line is an output from the FDC to the PLL.  Some systems do not use it
other use it as specified.

Allison


>Thanks,
>-- 
>Phil.
>classiccmp at philpem.me.uk
>http://www.philpem.me.uk/