Who wants to help read a Saturn V core stack?

[Paul_Koning at Dell.com]

> Although, not described in most books on cores, the inhibit lines
>were quite common. The use made it so that there was greater
>margine between the signal level of the address line running through
>the row or column bit that were not addressed and the one
>bit the that was to be read or written.

That doesn't sound right.

The fundamental property of core memory is that the cores have a threshold flux level (hence magnetizing current level) that causes them to flip state, while currents modestly below the threshold (like 1/2 of it) have no effect.

A "concident current" core memory has a grid of X and Y wires for addressing.  The word address is split in half.  One part selects one of the X wires, the other one of the Y wires.  Each selected wire receives a current pulse half the threshold current.  Result: the addressed core (at the intersection of the two selected wires) flips state to match the direction of magnetization for the X/Y currents, if it wasn't already in that state.

For a read, the current direction is one way which is defined to represent zero.  If the addressed core was in the "one" state, the state flip induces a current into the "sense" wire -- which runs through all the cores in the plane.  So read is actually "read and clear".

For a write, the current direction is the other way, representing "one".  Write is done after read, and only to the planes of the core where you want a 1 bit in that word.

So in the simplest case, you end up having to have per-plane control over the X/Y drivers to select whether a write will write a 1 (current is on) or a 0 (no action).

The inhibit wire offers a different approach.  In that case, the X/Y drivers simply select the word, and are unconditionally on for both read and write.  To determine whether a 1 bit or a 0 bit will be written, the inhibit current is either off, or on, respectively.

The inhibit current runs opposite the X/Y current.  So if the inhibit current is off, the core at the X/Y intersection sees 0.5 + 0.5 times the threshold current, or 1x, so it flips state (to "one" in the case of a write).  If the inhibit current is on, the core at the X/Y intersection sees 0.5 + 0.5 - 0.5 times the threshold, or 0.5, so it does not change state.

None of this has anything to do with margin.  Coincident core memory is absolutely dependent on the property that the 0.5 current level doesn't change the core state.  Instead, the inhibit scheme simplifies the circuitry.

I've seen some variants.  The CDC 6000 series core memory doesn't use one inhibit wire, but rather two per core (so 5 wires per core total: X, Y, two inhibits, and sense).  The memory plane is split into 16 squares (4 x 4).  There are four separate "X" inhibit wires and four "Y" inhibits.  So the word address does two things: it selects a specific X and Y address wire, and two of X and two of the Y bits select a specific pair of inhibit wires.  I think the reason for doing this is to reduce the inductance of the inhibit wires (they only pass through 1024 cores rather than the full 4096) which allows higher speed operation.  And the use of pairs of inhibit wires means that each inhibit wire carries 0.25 times the threshold current, which may also help the drive circuitry.

One of these days I should take some of the material from the old (apparently uncopyrighted) 6600 training manual and adapt it for the core memory article in Wikipedia...

	paul