John Floren slawmaster at gmail.com
Thu Jan 15 12:25:46 CST 2009

On Wed, Jan 14, 2009 at 6:46 PM, Guy Sotomayor <ggs at shiresoft.com> wrote:
> Actually, he's gotten pretty far on it.  I just talked to him today about
> it.  I'd have to go back and look at my e-mail archives but late Nov/Dec he
> had it passing all of the DEC CPU diagnostics on a verilog simulator.  Today
> he told me how many FFs & LUTs it took (not as much as he thought) to
> implement a KA10 style CPU (so he's doing synthesis).
> TTFN - Guy
> On Jan 14, 2009, at 3:25 PM, Al Kossow wrote:
>> > Both Neil Franklin and
>> > Doug Conroy have done work in this area.
>> Dave Conroy.
>> He's not had time to work on it for a while now.

Promising! I've wanted to see a -10 in FPGA for a while now, never had
the ambition (or the hardware) to try writing one in VHDL or anything.
Good luck to Dave, I guess.


"I've tried programming Ruby on Rails, following TechCrunch in my RSS
reader, and drinking absinthe. It doesn't work. I'm going back to C,
Hunter S. Thompson, and cheap whiskey." -- Ted Dziuba

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