SC/MP 8073 addressing query

Doug Jackson doug at
Tue Jan 20 16:26:13 CST 2009

Hi list,

I have an interesting question regarding the INS8073 (National 
Semiconductor SC/MP 3 with BASIC in ROM).

Finally, somebody gave me a round tuit, and I have started work on a 
simple 8073 system.

Eventually, it will have 8K of ROM, 8K of RAM, an 8255, and a switch / 
LED interface. Currently on the board, I have the 6264 RAM tied to the 
8073, with no address decoding (ie the CS* on the RAM is tied to A15 on 
the CPU).  Sadly, as a simple test, this does not operate as I would 
expect.  I would have expected that the RAM would have been selected 
anywhere in the lower 32K or the memory map, and I would have a simple 
system that would spit out a console prompt.  But no luck.

Now the question....  The internal ROM is located in the lowest 4K or 
the memory map.  When the CPU is fetching data from the lower 4K, does 
it assert the NRDS line, and sample the external bus?  My belief is that 
it does not, as the trivial application note that I have seen simply 
ties a couple of 2114 to the processor, and uses A10 as the chip select.

Any ideas?


Doug Jackson, I-RAP, MAIPM, MIEEE

Principal Information Security Consultant
PO Box 6308 O'Connor ACT 2602
Level 1, 214 Northbourne Ave, Braddon ACT 2612
Tel: +61 (0)2 6230 6833
Fax: +61 (0)2 6230 5833
Mob: +61 (0)414 986 878


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