EPROM erase times and lifespan

Tony Duell ard at p850ug1.demon.co.uk
Fri Jan 30 13:10:41 CST 2009

> ISTR someone asked why higher-capacity chips take longer to erase. Newer chips 
> use smaller transistors -- the smaller the transistors, the smaller the 
> "floating gate" is, and the less SiO2 there is to be hit by the UV. Less area 
> = less energy absorbed = less charge leakage = longer erase time.

Yes, but I would have thought that smaller devices had less charge to 
discharge (if you see what I mean). Assuming the voltage on the floating 
gate is much the same in both cases (and if anything it'd be smaller on 
later/higher capacity devices), the charge is going to be roughly 
proportional to the area of the floating gate (since the capacitance 
between that gate and whatever you reference it to is proportional to 
that area).

I believe that if you have a number of charged bodies in a mediaum of 
resistivity rho and permitivity epsilon (as normal), the time constant of 
that system (to equalise the charges) is independnat of the shapes and 
positions of the charged bodies, it is simply rho * epsilion.

th return ot the 'intellegent' EPROM ereaser, my worried is that do we 
_know_ that the rest of the chip (addresss decoder, sense amplifiers, 
etc) will work correcting when irradiated with short-wavelength UV? In 
other words is the readout of the chip even meaningful under such conditions?


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