the arrogance of youth [was RE: UNIX V7]

[Brad Parker]

Guy Sotomayor wrote:
>
>Actually one of the guys I work with has done an FPGA design of a  
>PDP-10.  He's partitioned it into 3 Xilinix parts.  It passes all of  
>the DEC CPU diagnostics on a Verilog simulator.  He's talked a little  
>bit about it on alt.sys.pdp10.  He figures by using Spartan 3E parts  
>and not doing a lot of optimization he can get ~30-40MHz out of it  
>with no problems (ie trying to go faster would take a lot of work and/ 
>or much more expensive FPGAs).

microcode or direct decode?
any i or d cache?
how deep is the pipe? (or, any pipelining at all?)

and, the most important part, will he release the verilog?

-brad