fpga pdp's; [was Re: ...arrogance [was RE: UNIX V7] ]
bob at theadamsons.co.uk
Wed Jun 17 13:03:13 CDT 2009
Eric Smith wrote:
>> Brad Parker wrote:
>>> I did a "direct decode" pdp-11 in verilog recently just to see how
>>> big it would be (and because I was frustrated with the pop-11
>>> project). It fits nicely & boots RT11 at 50mhz.
>> At that speed, surely it hasn't finished booting RT11 yet!
> sorry, I don't get the joke. clock is 50mhz, or 20ns; each state is one
> clock and on average
> an instruction is 3 states. I calculated 10mips. it seems to boot much
> faster than my 11/44 :-)
> what did I miss?
Possibly a pedant distinguishing (correctly) between mega and milli? ;o)
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