cctech Digest, Vol 78, Issue 3
keithvz at verizon.net
Sun Feb 7 16:57:09 CST 2010
> See: CPLD design. This current design is CPLD/2901 bitslice design.
> The ALU is 12 bits, double clocked to give a 24 bit CPU on a 6800/6502
> style memory cycle.One CPLD is for high speed decoding and the other
> for the MAR and MBR data paths. A 8 bit refresh counter is for DRAM's. A
> 2.5 MHZ (top speed)clock gives a 800 ns memory cycle. 3 2901's make
> up the data path.
> A LSI version would have 24 bits in the ALU, but with a 3 bit carry
> skip adder. The logic design is slow but simple, with decoding taking
> the first clock cycle and the second cycle for alu operations.
Neat. Is this on the order of 2000 gates +/-? I was trying to lookup
the number of gates on the Z80 and 680x, and this is the closest I could
Are you using verilog, VHDL, or something else? I have a Spartan-3e
starter kit that contains a CoolRunner™-II CPLD (XC2C64A-5VQ44C). I'm
in the process of using the FPGA, but haven't touched the CPLD. I
barely know how to spell it. :)
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