cpld design

[Philip Pemberton]

Ben wrote:
> I am using 128 cell CPLD's, from Atmel with CPUL (wincpul) for
> logic design. This language is at the gate level, but easy to use
> compared to the other two design languages.

Interesting. I find Verilog easier to use than CUPL. Certainly for 
register-based logic it makes the function of the code a bit more 
obvious; for combinational logic it really doesn't matter (although 
Verilog uses C-style expressions and thus might be a little easier for 
your average software geek to understand... ahem :P )

VHDL on the other hand is evil, distilled into its purest form. In my 
experience, what can be said in half a dozen lines of Verilog takes 30 
or so in VHDL. CUPL seems to sit somewhere in the middle.

I was forced to learn to read VHDL at a previous job (some idiot lost 
the register documentation for a glue-logic PLD, I got to rewrite it 
from source). That experience and one or two like it have put me off 
VHDL for life!

I do, however, still use CUPL on occasion for creating fusemaps for 
GALs... I think I've still got half a tube of DIL-packaged Lattice 
GAL16V8s in my spares bin...

-- 
Phil.
classiccmp at philpem.me.uk
http://www.philpem.me.uk/