cclist at sydex.com
Sun Feb 7 18:45:06 CST 2010
On 8 Feb 2010 at 0:31, Philip Pemberton wrote:
> VHDL on the other hand is evil, distilled into its purest form. In my
> experience, what can be said in half a dozen lines of Verilog takes 30
> or so in VHDL. CUPL seems to sit somewhere in the middle.
VHDL is the ADA of EDA languages--almost no one ever uses it because
they *want* to. I like Verilog very much; it's straightforward and
not too "dirty".
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