VHDL vs Verilog

Jos Dreesen jdr_use at bluewin.ch
Mon Feb 8 00:28:11 CST 2010


Chuck Guzis wrote:
> On 8 Feb 2010 at 0:31, Philip Pemberton wrote:
>
>   
>> VHDL on the other hand is evil, distilled into its purest form. In my
>> experience, what can be said in half a dozen lines of Verilog takes 30
>> or so in VHDL. CUPL seems to sit somewhere in the middle.
>>     
>
> VHDL is the  ADA of EDA languages--almost no one ever uses it because 
> they *want*  to.  I like Verilog very much; it's straightforward and 
> not too "dirty".
>
> --Chuck
>   


VHDL vs Verilog is another holy war, and about as useful as a 6502 vs 
Z80 discussion. Thus I continue :
Personally I pity those who never get into VHDL and stay with Verilog, 
and I will choose VHDL over Verilog any day.
Oh the agony when forced to use  a Verilog testbench from our US  
collegues.....


             Jos Dreesen






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