VHDL vs Verilog

[Ben]

Chuck Guzis wrote:
> On 8 Feb 2010 at 7:28, Jos Dreesen wrote:
>
>> VHDL vs Verilog is another holy war, and about as useful as a 6502 vs
>> Z80 discussion. Thus I continue : Personally I pity those who never
>> get into VHDL and stay with Verilog, and I will choose VHDL over
>> Verilog any day. Oh the agony when forced to use  a Verilog testbench
>> from our US  collegues.....
>
> I remember the Algol-FORTRAN cross-pond war of the 60s and 70s.  :)
>
> Now I wonder, "who won?"  :)
>
> --Chuck
>
I say fortran ...  They have compilers for it! :)
I think they have the same problem with the very high level
languages: NO IN/OUT.
Ben.