yet another pdp-11 in fgpa

[Walter F.J. Mueller]

Johnny Billquist <bqt at softjar.se> wrote:
 >>..
 >> "Walter F.J. Mueller" <w.f.j.mueller at gsi.de> wrote:
 >> At some later time maybe I'll try a really fast design, with separate
 >> instruction and data caches and significantly more parallelism than
 >> the J11 had.
 > Hmm. I wonder if that might cause headaches? There might be code out
 > there that require your i-cache and d-cache to be consistent with each
 > other.

sure, there is self modifying code. The maindec zkdjb2 for example has
a sequence like
    mov    #000240,(pc)
    jmp    (r1)
and tests that the 'nop' was executed and not the 'jmp'. However, the
cache, even separate i-d, is only one aspect, main point is to get
all the different 'write-after-read' hazards in the pipeline under
control. That's why I stayed with a simple 'prefetch-only' 11/70-like
implementation in the first round. Even in that case one has to be
careful and suppress for example the prefetch when the destination is
pc. Otherwise a 'clr pc',often found at the end of primary bootstraps,
will not do a 'jmp @#000000' but execute the opcode after the 'clr pc'.

	Walter