semi-OT: do you routinely attempt projects out of your comfort zone?

Keith keithvz at verizon.net
Thu Mar 11 11:48:29 CST 2010


Brad Parker wrote:

> Also, knowing a lot about 20V10 CPLD's isn't very much in call.  But being able to bring up the internal
> PPC's in a Virtex 2 was a helpful skill over the past 5 years, especially if you knew how to do it in modelsim.
> So, turns out that playing with verilog and various simulators was a good use of my time.

And so you have hit on my current frustration.  Verilog, FGPAs, 
simulators, all this stuff.  Fairly steep learning curve despite having 
some related background skills.  I've been pretty unhappy with the 
quality of books, online materials, forums, etc.

With books, I'm particularly sensitive to the way in which material is 
presented -- I like practical and useful knowledge.  Once we start 
getting too abstract, I start losing interest and don't know WHY I'm 
reading this stuff.  It hardly seems related if I can't apply what I'm 
reading.

I've been very lucky to find ONE person I work with, who does this stuff 
(albeit in VHDL) for a living, who has the patience, desire to help, and 
  excellent understanding of the subject.  I find myself struggling w/ 
the vocabulary to explain concisely my issues.  This person is a saint. :)

  > (did I mention writing microcode is fun? :-)

Is this Microblaze, or Picoblaze, or NIOS?

> I have found that if you are not completely sick of a project, it's not done.  By the time it is done you are sick of looking at it,
> mostly because the last 20% take forever and requires herculean perseverance.  But when it's done you've learned a lot
> and you have something to show for your efforts.

I've had this 5-year project that refuses to die.  It's probably an 
undergraduate level project that most students would do in a month or 
something.  The slow progress is honestly embarrassing.  I don't 
dedicate much time to it, but that's barely an excuse.

Thanks for the reply.

Keith



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