MIPS CPUs

[Philip Pemberton]

(Taking this into a separate thread, it has nothing to do with disc 
analysers).

Cameron Kaiser wrote:
>> As I understand it, you can design a MIPS chip based on the published 
>> specs and not have to pay any licensing fees. There was a patent on the 
>> unaligned load/store instructions, but that expired in 2006 AIUI.
> 
> That's probably why the Chinese have jumped on it (Godson/Loongson), not
> that they worry excessively about licensing, but anyway.

It's probably why there are so many open-source MIPS cores on Opencores 
too. I've been playing with UCore this evening and tweaked it to run at 
about 80MHz on an Altera Cyclone II. Unfortunately the feature list on 
Opencores is for a newer version of the code, which was apparently never 
uploaded :(

I've got a few 'suspended projects' that would benefit from having a 
reasonably fast (~100MHz would be nice, ideally with a bit of I-cache 
and D-cache), 32-bit RISC CPU core with decent compiler/RTOS support. 
Ucore seems to fit the bill (although there are reports that it doesn't 
work properly) but the "older version" of the code has support for 
instruction or data caching :( :(

(That and I'll need to rig up some form of bus arbitration scheme to 
merge the Instruction and Data buses together... now won't that be fun.. 
at least it's WISHBONE compliant, I suppose)

-- 
Phil.
classiccmp at philpem.me.uk
http://www.philpem.me.uk/