MIPS CPUs

[Philip Pemberton]

e.stiebler wrote:
> Did you check YARI ?

You mean this?
http://yari.thorn.ws/YARI/Status.html

Well it's cached, but doesn't have any support for Supervisor mode or 
the WISHBONE bus, which means I'll (at the very least) have to write a 
bus translator if I want to make it talk to a WISHBONE-compliant device. 
The shared instruction/data bus is a nice addition -- will be nice to 
get rid of the bus arbitration logic.

The lack of an illegal instruction trap is somewhat concerning, though...

-- 
Phil.
classiccmp at philpem.me.uk
http://www.philpem.me.uk/