Ones' complement adder/subtractor

[Eric Smith]

  Dwight asks:
 > Haaa! Evil FPGA!
 > Would it be possible to put two half adders in a single LUT? Dwight

Generally not.  Traditional Xilinx FPGAs, such as the Virtex-4 and 
Spartan-3 families, use a logic element that consists of a 4-LUT 
(four-input Look-Up Table) and a flip-flop.  (You don't have to use the 
flip-flop.)  There are some added complications such as the dedicated 
carry logic chain.  The 4-LUT is a 16-word 1-bit RAM, and gets loaded 
when the FPGA is configured. It can generate a single boolean function 
of up to four inputs.

The reason I say "generally not" is that recent Xilinx FPGAs, such as 
the Virtex-5, Virtex-6, and Spartan-6, use what Xilinx calls a 6-LUT, 
with two flip-flops.  This can be used as two 5-LUTs to generate two 
functions of five inputs, provided that the same five inputs are shared 
between both functions.  You actually could put two half-adders into one 
of these 6-LUTs, if you didn't want to take advantage of the dedicated 
carry logic chain.  However, the dedicated carry logic chain is much 
faster than the usual through-the-fabric routing, so if you need your 
one's complement adder to have high performance, you won't want to do it 
that way.

Eric